公开(公告)号：US20240276703A1

公开(公告)日：2024-08-15

申请号：US18517126

申请日：2023-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonsok Lee ,  Juho Lee ,  Seunghyun Kim ,  Wooje Jung ,  Minhee Cho

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/033 ,  H10B12/05

Abstract: A semiconductor memory device, which may include a substrate, a lower conductive line on the substrate, an isolation insulating layer on the lower conductive line and including a channel trench, a channel structure inside the channel trench and including a first oxide semiconductor material, an interfacial conductive pattern between the lower conductive line and a lower surface of the channel structure, a gate dielectric layer that covers the channel structure within the channel trench, an upper conductive line on the gate dielectric layer within the channel trench, a conductive contact pattern on the channel structure, an interfacial oxide semiconductor pattern between the channel structure and the conductive contact pattern and including a second oxide semiconductor material, and a capacitor structure including a lower electrode connected to the conductive contact pattern.