公开(公告)号：US11871558B2

公开(公告)日：2024-01-09

申请号：US17963591

申请日：2022-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jae Hoon Kim ,  Kwang-ho Park ,  Seungjae Jung

IPC: H01L29/786 ,  H10B12/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/285

CPC classification number: H10B12/30 ,  H01L21/02603 ,  H01L21/28518 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696 ,  H10B12/01 ,  H10B12/05 ,  H10B12/482 ,  H10B12/50

Abstract: A semiconductor memory device includes a stack structure comprising a plurality of layers vertically stacked on a substrate, each layer including a semiconductor pattern, a gate electrode extending in a first direction on the semiconductor pattern, and a data storage element electrically connected to the semiconductor pattern, a plurality of vertical insulators penetrating the stack structure, the vertical insulators arranged in the first direction, and a bit line provided at a side of the stack structure and extending vertically. The bit line electrically connects the semiconductor patterns which are stacked. Each of the vertical insulators includes first and second vertical insulators adjacent to each other. The gate electrode includes a connection portion disposed between the first and second vertical insulators.

公开(公告)号：US11751379B2

公开(公告)日：2023-09-05

申请号：US17731611

申请日：2022-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hoon Kim ,  Kwang-Ho Park ,  Yong-Hoon Son ,  Hyunji Song ,  Gyeonghee Lee ,  Seungjae Jung

IPC: G11C5/06 ,  H10B12/00 ,  G11C11/4097

CPC classification number: H10B12/30 ,  G11C11/4097

Abstract: A semiconductor memory device may include a bit line extending in a first direction, a first conductive pattern extending in a second direction intersecting the first direction, a semiconductor pattern connecting the bit line and the first conductive pattern, a second conductive pattern including an insertion portion in the first conductive pattern, and a dielectric layer between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width which increases as a distance from the semiconductor pattern increases.

公开(公告)号：US11462554B2

公开(公告)日：2022-10-04

申请号：US16857507

申请日：2020-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jae Hoon Kim ,  Kwang-ho Park ,  Hyunji Song ,  Gyeonghee Lee ,  Seungjae Jung

IPC: H01L27/11565 ,  H01L27/11573 ,  H01L27/1157 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11582

Abstract: A semiconductor memory device is disclosed. The device includes a peripheral circuit structure on a substrate, a semiconductor layer on the peripheral circuit structure, an electrode structure on the semiconductor layer, the electrode structure including electrodes stacked on the semiconductor layer, a vertical channel structure penetrating the electrode structure and being connected to the semiconductor layer, a separation structure penetrating the electrode structure, extending in a first direction, and horizontally dividing the electrode of the electrode structure into a pair of electrodes, an interlayered insulating layer covering the electrode structure, and a through contact penetrating the interlayered insulating layer and being electrically connected to the peripheral circuit structure.

公开(公告)号：US11437380B2

公开(公告)日：2022-09-06

申请号：US16898640

申请日：2020-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang-Ho Park ,  Jae Hoon Kim ,  Yong-Hoon Son ,  Seung Jae Jung

IPC: H01L27/06 ,  H01L27/108 ,  H01L21/768

Abstract: A semiconductor memory device including first-first conductive lines on a substrate; second-first conductive lines on the first-first conductive lines; first contacts connected to the first-first conductive lines; and second contacts connected to the second-first conductive lines, wherein the first-first conductive lines protrude in a first direction beyond the second-first conductive lines; the first-first conductive lines include first regions having a first thickness, second regions having a second thickness, the second thickness being greater than the first thickness, and third regions having a third thickness, the third thickness being smaller than the first thickness and smaller than the second thickness, and the second regions of the first-first conductive lines are between the first regions of the first-first conductive lines and the third regions of the first-first conductive lines.

公开(公告)号：US11348924B2

公开(公告)日：2022-05-31

申请号：US16923572

申请日：2020-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hoon Kim ,  Kwang-Ho Park ,  Yong-Hoon Son ,  Hyunji Song ,  Gyeonghee Lee ,  Seungjae Jung

IPC: G11C5/06 ,  H01L27/108 ,  G11C11/4097

Abstract: A semiconductor memory device may include a bit line extending in a first direction, a first conductive pattern extending in a second direction intersecting the first direction, a semiconductor pattern connecting the bit line and the first conductive pattern, a second conductive pattern including an insertion portion in the first conductive pattern, and a dielectric layer between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width which increases as a distance from the semiconductor pattern increases.

公开(公告)号：US10971516B2

公开(公告)日：2021-04-06

申请号：US16294425

申请日：2019-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Soo Ahn ,  Yong-Hoon Son ,  Minhyuk Kim ,  Jae Ho Min ,  Daehyun Jang

IPC: H01L27/11582 ,  H01L21/28 ,  H01L27/11565 ,  H01L21/311 ,  H01L27/1157

Abstract: Integrated circuit devices and methods of forming the same are provided. The devices may include a substrate including a cell region and an extension region and conductive layers stacked on the cell region in a vertical direction. The conductive layers may extend onto the extension region and may have a stair-step structure on the extension region. The devices may also include vertical structures on the substrate. Each of the vertical structures may extend in the vertical direction, and the vertical structures may include a first vertical structure on the cell region and a second vertical structure on the extension region. The first vertical structure may extend through the conductive layers and may include a first channel layer, the second vertical structure may be in the stair-step structure and may include a second channel layer, and the second channel layer may be spaced apart from the substrate in the vertical direction.

公开(公告)号：US10553582B2

公开(公告)日：2020-02-04

申请号：US15413466

申请日：2017-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoonjae Kim ,  Cheol Kim ,  Yong-Hoon Son ,  Jin-Hyuk Yoo ,  Woojin Jung

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/485 ,  H01L21/768 ,  H01L21/306 ,  H01L21/311 ,  H01L27/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/165

Abstract: A semiconductor device includes a substrate having an active pattern, a conductive pattern crossing the active pattern, a spacer structure on at least one side surface of the conductive pattern, and a capping structure on the conductive pattern. The capping structure includes a first capping pattern and a second capping pattern. The second capping pattern is disposed on a top surface of the first capping pattern and a top surface of the spacer structure.

公开(公告)号：US09496277B2

公开(公告)日：2016-11-15

申请号：US14723644

申请日：2015-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

IPC: H01L21/336 ,  H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  H01L27/105 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/306 ,  H01L21/3213 ,  H01L29/423

CPC classification number: H01L27/11582 ,  H01L21/02524 ,  H01L21/02587 ,  H01L21/02598 ,  H01L21/02675 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/32133 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1158 ,  H01L29/4234 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/66787 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.

公开(公告)号：US20130065381A1

公开(公告)日：2013-03-14

申请号：US13673396

申请日：2012-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Jong- Wook Lee ,  Jong-Hyuk Kang

IPC: H01L21/20

CPC classification number: H01L27/11582 ,  H01L21/02524 ,  H01L21/02587 ,  H01L21/02598 ,  H01L21/02675 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/30604 ,  H01L21/32133 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1158 ,  H01L29/4234 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66666 ,  H01L29/66787 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

Abstract: In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.

公开(公告)号：US11950405B2

公开(公告)日：2024-04-02

申请号：US17752921

申请日：2022-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son

IPC: H01L27/108 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B12/00

CPC classification number: H10B12/30 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696 ,  H10B12/03 ,  H10B12/05 ,  H10B12/482

Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory devices may include a plurality of layers sequentially stacked on a substrate in a vertical direction, each of the plurality of layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction traversing the first direction, a gate electrode extending through the plurality of layers and including a vertical portion extending through the semiconductor patterns and a first horizontal portion extending from the vertical portion and facing a first surface of one of the semiconductor patterns, and a data storing element electrically connected to the one of the semiconductor patterns. The data storing element includes a first electrode electrically connected to the one of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes.