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公开(公告)号：US12033701B2
公开(公告)日：2024-07-09
申请号：US18123302
申请日：2023-03-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youn-Yeol Lee , Wook-Ghee Hahn
CPC classification number: G11C16/24 , G11C7/1039 , G11C16/0433 , G11C16/10 , G11C16/26
Abstract: A non-volatile memory device includes an upper semiconductor layer including a first metal pad and vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a second metal and a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group. The upper semiconductor layer is vertically connected to the lower semiconductor layer by the first metal pad and the second metal pad.
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公开(公告)号：US11164638B2
公开(公告)日：2021-11-02
申请号：US17014511
申请日：2020-09-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youn-Yeol Lee , Wook-Ghee Hahn
Abstract: A non-volatile memory device includes an upper semiconductor layer including a first metal pad and vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a second metal and a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group. The upper semiconductor layer is vertically connected to the lower semiconductor layer by the first metal pad and the second metal pad.
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公开(公告)号：US12073888B2
公开(公告)日：2024-08-27
申请号：US18123302
申请日：2023-03-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youn-Yeol Lee , Wook-Ghee Hahn
CPC classification number: G11C16/24 , G11C7/1039 , G11C16/0433 , G11C16/10 , G11C16/26
Abstract: A non-volatile memory device includes an upper semiconductor layer including a first metal pad and vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a second metal and a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group. The upper semiconductor layer is vertically connected to the lower semiconductor layer by the first metal pad and the second metal pad.
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公开(公告)号：US10790291B2
公开(公告)日：2020-09-29
申请号：US16241095
申请日：2019-01-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youn-Yeol Lee , Wook-Ghee Hahn
IPC: G11C16/24 , H01L27/11524 , H01L27/11551 , H01L27/112 , G11C16/08 , G11C16/04 , G11C7/10 , G11C5/02
Abstract: A non-volatile memory device includes an upper semiconductor layer vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group.
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Patent Agency Ranking
公开(公告)号：US11631465B2
公开(公告)日：2023-04-18
申请号：US17495645
申请日：2021-10-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youn-Yeol Lee , Wook-Ghee Hahn
Abstract: A non-volatile memory device includes an upper semiconductor layer including a first metal pad and vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a second metal and a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group. The upper semiconductor layer is vertically connected to the lower semiconductor layer by the first metal pad and the second metal pad.
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公开(公告)号：US10797066B2
公开(公告)日：2020-10-06
申请号：US16030170
申请日：2018-07-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youn-Yeol Lee , Chanho Kim
IPC: H01L27/11575 , H01L27/11573 , H01L27/11582 , H01L27/1157 , G11C16/04
Abstract: A memory device includes a substrate, a first memory structure including a plurality of first word lines stacked on the substrate in a direction perpendicular to a top surface of the substrate, an inter-metal layer on the first memory structure and including a plurality of intermediate pads connected with separate, respective first word lines of the plurality of first word lines, a second memory structure including a plurality of second word lines stacked on the inter-metal layer in the direction perpendicular to the top surface of the substrate, and an upper metal layer on the second memory structure and including a plurality of upper pads connected with separate, respective second word lines of the plurality of second word lines.
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公开(公告)号：US10770150B2
公开(公告)日：2020-09-08
申请号：US16181176
申请日：2018-11-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youn-Yeol Lee , Wook-Ghee Hahn
Abstract: In a method of reading initialization information from a non-volatile memory device, when power-up is detected, the non-volatile memory device divides a source voltage to generate a low read pass voltage which is to be provided to unselected word lines in an initialization information read operation. The low read pass voltage is set as at least one voltage between a ground voltage and the source voltage. The non-volatile memory device allows the source voltage not to be pumped in the initialization information read operation, based on the power-up. In the initialization information read operation, the non-volatile memory device provides the low read pass voltage to the unselected word lines and provides a read voltage to a selected word line to read initialization information stored in the memory cells.
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公开(公告)号：US11823888B2
公开(公告)日：2023-11-21
申请号：US17025300
申请日：2020-09-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youn-Yeol Lee , Chanho Kim
IPC: H01L25/18 , H01L25/065 , H01L23/00
CPC classification number: H01L25/18 , H01L24/08 , H01L25/0657 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
Abstract: A memory device includes a peripheral circuit layer, a first memory layer provided on the peripheral circuit layer, an inter-metal layer provided on the first memory layer, and a second memory layer provided on the inter-metal layer. The peripheral circuit layer includes a first substrate and a peripheral circuit provided on the first substrate. The first memory layer includes a first memory structure electrically connected to the peripheral circuit through metal bonding pads. The inter-metal layer includes intermediate pads electrically connected to the peripheral circuit through metal bonding pads. The second memory layer includes a second memory structure electrically connected with the intermediate pads and a second substrate provided on the second memory structure. The peripheral circuit, the first memory structure, and the second structure are provided between the first substrate and the second substrate.
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公开(公告)号：US10998052B2
公开(公告)日：2021-05-04
申请号：US16996210
申请日：2020-08-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youn-Yeol Lee , Wook-Ghee Hahn
Abstract: In a method of reading initialization information from a non-volatile memory device, when power-up is detected, the non-volatile memory device divides a source voltage to generate a low read pass voltage which is to be provided to unselected word lines in an initialization information read operation. The low read pass voltage is set as at least one voltage between a ground voltage and the source voltage. The non-volatile memory device allows the source voltage not to be pumped in the initialization information read operation, based on the power-up. In the initialization information read operation, the non-volatile memory device provides the low read pass voltage to the unselected word lines and provides a read voltage to a selected word line to read initialization information stored in the memory cells.
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