公开(公告)号：US20250126835A1

公开(公告)日：2025-04-17

申请号：US18625457

申请日：2024-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongjin LEE ,  Min Tae RYU ,  Younggeun SONG ,  Sanghoon AHN ,  Min Hee CHO ,  Daewon HA

IPC: H01L29/786 ,  H01L29/66

Abstract: A semiconductor device may include peripheral circuit structures on a substrate, an interlayer insulating layer on the peripheral circuit structure, a bit line extending in a first direction in the interlayer insulating layer, a semiconductor pattern on the bit line, and including first and second vertical portions facing each other in the first direction and a horizontal portion connecting the first and second vertical portions to each other, first and second word lines on the horizontal portion and adjacent to the first and second vertical portions, respectively, and a gate insulating pattern interposed between the first vertical portion and the first word line, and between the second vertical portion and the second word line. An upper surface of the interlayer insulating layer and an upper surface of the bit line are coplanar with each other.

公开(公告)号：US20240373621A1

公开(公告)日：2024-11-07

申请号：US18627685

申请日：2024-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungmin SHIN ,  Kijong PARK ,  Sangjun PARK ,  Younggeun SONG ,  Ilyoung YOON ,  Yongjin LEE

IPC: H10B12/00

Abstract: In a method for manufacturing a semiconductor device, comprising; forming mold insulation patterns on a substrate, forming an oxide semiconductor layer conformally on sidewalls and upper surfaces of the mold insulation patterns and the substrate, forming a first metal oxide layer on the oxide semiconductor layer, patterning the first sacrificial layer, the first metal oxide layer, and the oxide semiconductor layer to form a first structure including a preliminary first metal oxide layer pattern, a preliminary oxide semiconductor layer pattern and a first sacrificial layer pattern stacked, forming a preliminary second metal oxide layer pattern selectively on a sidewall of the preliminary oxide semiconductor layer pattern, removing selective portions of the first structure and the preliminary second metal oxide layer pattern to form an oxide semiconductor layer pattern, a first metal oxide layer pattern, and a second metal oxide layer pattern.

公开(公告)号：US20240244831A1

公开(公告)日：2024-07-18

申请号：US18239268

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younggeun SONG ,  Sanghoon UHM ,  Yongjin LEE ,  Min Hee CHO

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/02 ,  H10B12/315 ,  H10B12/488 ,  H10B12/50

Abstract: A semiconductor device includes a bit line extending in a first direction on a substrate. A first insulating pattern is disposed on the bit line. A channel pattern is disposed on an upper side of the bit line and a lateral side of the first insulating pattern. The channel pattern includes an oxide semiconductor material. A gate insulating pattern is disposed on the channel pattern. Word lines are disposed on the gate insulating pattern. A second insulating pattern is disposed on the word lines. A landing pad is disposed on the channel pattern. An interlayer insulating layer disposed between the bit line and the channel pattern.