公开(公告)号：US11658853B2

公开(公告)日：2023-05-23

申请号：US17680583

申请日：2022-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghwan Chang ,  Eun-Young Jin ,  Youngseo Kim ,  Kilhoon Lee ,  Hyunwook Lim ,  Seng-Sub Chun

IPC: H04L27/01 ,  H04B17/21

CPC classification number: H04L27/01 ,  H04B17/21

Abstract: An operation method of a receiver, which includes setting a coefficient of an equalizer based on one of a plurality of first codes, setting a coefficient of an amplifier based on one of a plurality of second codes, performing offset calibration by driving the equalizer and the amplifier based on the coefficient of the equalizer and the coefficient of the amplifier, storing an offset code corresponding to a voltage offset generated when the equalizer and the amplifier are driven, determining whether the offset calibration is completed, performing a normal operation of obtaining reception data from an input signal, in response to determining that the offset calibration is completed, and removing the voltage offset based on the offset code, in the normal operation.

公开(公告)号：US11223468B1

公开(公告)日：2022-01-11

申请号：US17194831

申请日：2021-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungho Ryu ,  Kyongho Kim ,  Kilhoon Lee ,  Yeongcheol Rhee ,  Taeho Lee ,  Hyunwook Lim ,  Younghwan Chang ,  Sengsub Chun

IPC: H04L7/00 ,  H04L27/01

Abstract: A receiver circuit includes an equalizer configured to generate an equalization signal by equalizing an input data signal transferred through a communication channel based on an equalization coefficient; a clock data recovery circuit configured to generate a data clock signal and an edge clock signal based on the equalization signal, generate a data sample signal including a plurality of data bits by sampling the equalization signal in synchronization with the data clock signal, and generate an edge sample signal including a plurality of edge bits by sampling the equalization signal in synchronization with the edge clock signal; and an equalization control circuit configured to control the equalization coefficient by comparing the plurality of data bits and the plurality of edge bits.