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公开(公告)号:US20170250680A1
公开(公告)日:2017-08-31
申请号:US15438861
申请日:2017-02-22
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Roh YAMAMOTO
IPC: H03K3/0233
CPC classification number: H03K3/02337 , H03K3/3565 , H03K5/2481
Abstract: A hysteresis comparator that has a small circuit area and low power consumption is provided. A differential pair in the comparator is formed using transistors each including a back gate. The comparator is configured to apply an inverted signal of a logic value of an output signal of the comparator to the back gate of the transistor. That is, the threshold voltage of the transistor is controlled by the inverted signal. By the change of the threshold voltage, hysteresis can be added to an input comparison voltage.
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公开(公告)号:US20240048868A1
公开(公告)日:2024-02-08
申请号:US18382081
申请日:2023-10-20
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Roh YAMAMOTO
IPC: H04N25/77 , H01L27/146 , H04N25/46 , H04N25/71
CPC classification number: H04N25/77 , H01L27/1461 , H01L27/14616 , H04N25/46 , H04N25/745 , G06N3/02
Abstract: An imaging device that facilitates pooling processing. A pixel region includes a plurality of pooling modules and an output circuit, the pooling module includes a pooling circuit and a comparison module, the pooling circuit includes a plurality of pixels and an arithmetic circuit, and the comparison module includes a plurality of comparison circuits and a determination circuit. The pixel can obtain a first signal through photoelectric conversion, and can multiply the first signal by a given scaling factor to generate a second signal. The pooling circuit adds a plurality of second signals in the arithmetic circuit to generate a third signal, the comparison module compares a plurality of third signals and outputs the largest third signal to the determination circuit, and the determination circuit determines the largest third signal and binarizes it to generate a fourth signal. In the imaging device, the pooling module performs pooling processing in accordance with the number of pixels and outputs data obtained by the pooling processing.
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公开(公告)号:US20220385840A1
公开(公告)日:2022-12-01
申请号:US17851138
申请日:2022-06-28
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Roh YAMAMOTO
Abstract: An imaging device that facilitates pooling processing. A pixel region includes a plurality of pooling modules and an output circuit, the pooling module includes a pooling circuit and a comparison module, the pooling circuit includes a plurality of pixels and an arithmetic circuit, and the comparison module includes a plurality of comparison circuits and a determination circuit. The pixel can obtain a first signal through photoelectric conversion, and can multiply the first signal by a given scaling factor to generate a second signal. The pooling circuit adds a plurality of second signals in the arithmetic circuit to generate a third signal, the comparison module compares a plurality of third signals and outputs the largest third signal to the determination circuit, and the determination circuit determines the largest third signal and binarizes it to generate a fourth signal. In the imaging device, the pooling module performs pooling processing in accordance with the number of pixels and outputs data obtained by the pooling processing.
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公开(公告)号:US20200013320A1
公开(公告)日:2020-01-09
申请号:US16490956
申请日:2018-02-28
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Roh YAMAMOTO
Abstract: A test circuit is incorporated in an IC without an increase in a chip area. The IC includes a plurality of pins, a plurality of current sensing circuits, and a current generation circuit. The plurality of current sensing circuits process currents flowing through the plurality of pins in parallel and generates digital data, for example. The current generation circuit includes a capacitor and generates a reference current corresponding to the amount of electric charge of the capacitor. The amount of electric charge can be controlled by a voltage input to the capacitor, and thus the range of output currents for current generation can be made wide. The reference current is used for testing the plurality of current sensing circuits. The IC is used for a source driver IC of a display panel, for example. In this case, currents flowing through pixels in the display panel can be sensed by the plurality of current sensing circuits.
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公开(公告)号:US20180224961A1
公开(公告)日:2018-08-09
申请号:US15870141
申请日:2018-01-12
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Roh YAMAMOTO , Hideki UOCHI
CPC classification number: G06F3/044 , G09G3/2096 , G09G3/36 , G09G2300/0426 , G09G2300/0452 , G09G2300/0809 , G09G2300/0842 , G09G2310/0291 , G09G2310/08 , G09G2320/0613 , G09G2320/103 , G09G2330/021 , G09G2370/08 , G09G2370/14 , H01L29/78648 , H01L29/7869 , H01L29/78696
Abstract: A display device with less power consumption. The display device operates in a still image display period and a moving image display period, and includes a receiving circuit having a function of receiving an image signal, a driver circuit having a function of driving a display portion, and the display portion having a function of displaying an image. The display portion displays an image at a frame frequency of less than or equal to 1 Hz in the still image display period. The receiving circuit stops receiving an image signal in the still image display period. Switching from the still image display period to the moving image display period is accurately performed by an external signal.
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公开(公告)号:US20160070386A1
公开(公告)日:2016-03-10
申请号:US14844344
申请日:2015-09-03
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Roh YAMAMOTO , Hideki UOCHI
CPC classification number: G06F3/044 , G09G3/2096 , G09G3/36 , G09G2300/0426 , G09G2300/0452 , G09G2300/0809 , G09G2300/0842 , G09G2310/0291 , G09G2310/08 , G09G2320/0613 , G09G2320/103 , G09G2330/021 , G09G2370/08 , G09G2370/14
Abstract: A display device with less power consumption. The display device operates in a still image display period and a moving image display period, and includes a receiving circuit having a function of receiving an image signal, a driver circuit having a function of driving a display portion, and the display portion having a function of displaying an image. The display portion displays an image at a frame frequency of less than or equal to 1 Hz in the still image display period. The receiving circuit stops receiving an image signal in the still image display period. Switching from the still image display period to the moving image display period is accurately performed by an external signal.
Abstract translation: 具有较少功耗的显示设备。 显示装置在静止图像显示周期和运动图像显示周期中操作,并且包括具有接收图像信号的功能的接收电路,具有驱动显示部分的功能的驱动器电路以及具有功能的显示部分 显示图像。 显示部分在静止图像显示周期中以小于或等于1Hz的帧频率显示图像。 接收电路在静止图像显示周期中停止接收图像信号。 通过外部信号精确地执行从静止图像显示周期到运动图像显示周期的切换。
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公开(公告)号:US20210318856A1
公开(公告)日:2021-10-14
申请号:US17050359
申请日:2019-04-15
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Takayuki IKEDA , Roh YAMAMOTO , Shuichi KATSUI
IPC: G06F7/60 , H01L27/108 , H01L27/12 , H01L29/786 , G06F7/57 , G06N3/08
Abstract: A semiconductor device that updates a weight coefficient used for arithmetic operation by an artificial neural network is provided. Each of the first to third memory cells draws a current corresponding to data of its retention node and changes the data in accordance with the potentials of first and second wirings. When a weight coefficient and first and second reference data are held in the retention nodes of the first to third memory cells, the first circuit supplies, to a third wiring, a constant currents drawn by the second and third memory cells. When input data is input to the first wiring, a difference current between the constant current and a current drawn by the first memory cell is changed, and the second circuit outputs arithmetic result data corresponding to the change. The third circuit inputs update data corresponding to the arithmetic result data to the second wiring.
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公开(公告)号:US20210134860A9
公开(公告)日:2021-05-06
申请号:US16615156
申请日:2018-05-16
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Takayuki IKEDA , Yoshiyuki KUROKAWA , Shintaro HARADA , Hidetomo KOBAYASHI , Roh YAMAMOTO , Kiyotaka KIMURA , Takashi NAKAGAWA , Yusuke NEGORO
IPC: H01L27/146 , H04N5/341 , H04N5/374 , H01L29/786 , H04N5/3745 , H01L27/12
Abstract: An imaging device capable of image processing is provided.
The imaging device can retain analog data (image data) obtained by an image-capturing operation in a pixel and perform a product-sum operation of the analog data and a predetermined weight coefficient in the pixel to convert the data into binary data. When the binary data is taken in a neural network or the like, processing such as image recognition can be performed. Since enormous volumes of image data can be retained in pixels in the state of analog data, processing can be performed efficiently.-
公开(公告)号:US20190341913A1
公开(公告)日:2019-11-07
申请号:US16511042
申请日:2019-07-15
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Roh YAMAMOTO
IPC: H03K3/356 , G11C19/28 , G11C11/412 , G09G3/3233 , G09G3/36 , H03K19/0185 , G09G3/20 , H03K19/00 , H03K3/012
Abstract: An object is to provide a level shift circuit that operates stably. A semiconductor device includes a level shift circuit including first to fourth transistors and a buffer circuit. One of a source and a drain (S/D) of the first transistor is connected to one of a source and a drain of the second transistor. The other of the source and the drain of the second transistor is connected to one of a source and a drain of the third transistor. A gate of the first transistor and a gate of the fourth transistor are connected to the other of the source and the drain of the second transistor and the one of the source and the drain of the third transistor. A gate of the third transistor is connected to a wiring to which an input signal is input. An input terminal of the buffer circuit is connected to one of a source and a drain of the fourth transistor. An output terminal of the buffer circuit is connected to a gate of the second transistor and a wiring to which an output signal is output.
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公开(公告)号:US20180091121A1
公开(公告)日:2018-03-29
申请号:US15706984
申请日:2017-09-18
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Roh YAMAMOTO
CPC classification number: H03K3/356017 , G09G3/20 , G09G3/3233 , G09G3/3611 , G09G2310/0289 , G09G2310/0291 , G11C11/412 , G11C19/28 , H03K3/012 , H03K3/356139 , H03K19/0013 , H03K19/018521
Abstract: An object is to provide a level shift circuit that operates stably. A semiconductor device includes a level shift circuit including first to fourth transistors and a buffer circuit. One of a source and a drain (S/D) of the first transistor is connected to one of a source and a drain of the second transistor. The other of the source and the drain of the second transistor is connected to one of a source and a drain of the third transistor. A gate of the first transistor and a gate of the fourth transistor are connected to the other of the source and the drain of the second transistor and the one of the source and the drain of the third transistor. A gate of the third transistor is connected to a wiring to which an input signal is input. An input terminal of the buffer circuit is connected to one of a source and a drain of the fourth transistor. An output terminal of the buffer circuit is connected to a gate of the second transistor and a wiring to which an output signal is output.
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