公开(公告)号：US09466393B2

公开(公告)日：2016-10-11

申请号：US14997041

申请日：2016-01-15

Applicant: Jeong-kyoum Kim ,  Seok-hun Hyun ,  Jung-hwan Choi ,  Seong-jin Jang

Inventor： Jeong-kyoum Kim ,  Seok-hun Hyun ,  Jung-hwan Choi ,  Seong-jin Jang

IPC: G11C17/18 ,  G11C29/04 ,  G11C29/44 ,  G11C29/00 ,  G11C17/16 ,  G11C5/04 ,  G11C11/40

CPC classification number: G11C17/18 ,  G11C5/04 ,  G11C11/40 ,  G11C17/16 ,  G11C29/04 ,  G11C29/44 ,  G11C29/76 ,  G11C29/78 ,  G11C29/789 ,  G11C2029/4402

Abstract: A memory device capable of rescuing defective characteristics that occur after packaging includes a memory cell array including a plurality of memory cells and an antifuse circuit unit including at least one antifuse. The antifuse circuit unit stores a defective cell address of the memory cell array in the at least one antifuse and reads the defective cell address to an external source. The antifuse circuit unit stores a defective characteristic code in the at least one antifuse, wherein the defective characteristic code is related to at least one of a timing parameter spec., a refresh spec., an input/output (I/O) trigger voltage spec., and a data training spec. of the memory device, and outputs the defective characteristic code to an external source.

Abstract translation: 能够拯救包装后发生的缺陷特性的存储器件包括包括多个存储单元的存储单元阵列和包括至少一个反熔丝的反熔断电路单元。 反熔丝电路单元将存储单元阵列的缺陷单元地址存储在至少一个反熔丝中，并将缺陷单元地址读取到外部源。 反熔丝电路单元将不良特性代码存储在至少一个反熔丝中，其中不良特性代码与定时参数规格，刷新规格，输入/输出（I / O）触发电压 规格和数据训练规范。 并将缺陷特征码输出到外部源。

公开(公告)号：US07499370B2

公开(公告)日：2009-03-03

申请号：US11850754

申请日：2007-09-06

Applicant: Hyun-jin Kim ,  Ho-young Song ,  Youn-sik Park ,  Seong-jin Jang

Inventor： Hyun-jin Kim ,  Ho-young Song ,  Youn-sik Park ,  Seong-jin Jang

IPC: G11C8/00

CPC classification number: G11C7/1072 ,  G11C7/1057 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093

Abstract: A synchronous semiconductor memory device includes an output control signal generator, which generates an output control signal corresponding to a signal obtained by delaying a read information signal in response to a delay internal clock signal obtained by dividing an internal clock signal by n, first and second sampling signals obtained by delaying the internal clock signal, a first output control clock signal obtained by dividing the internal clock signal by n, and a column address strobe (CAS) latency signal. The synchronous semiconductor memory device also includes a data output buffer, which outputs data by buffering internal data in response to the output control signal and the first output control clock signal.

Abstract translation: 一个同步半导体存储器件包括一个输出控制信号发生器，它产生一个输出控制信号，该输出控制信号对应于通过将内部时钟信号除以n而获得的延迟内部时钟信号延迟读取信息信号获得的信号，第一和第二 通过延迟内部时钟信号获得的采样信号，通过将内部时钟信号除以n获得的第一输​​出控制时钟信号和列地址选通（CAS）等待时间信号。 同步半导体存储器件还包括数据输出缓冲器，其通过响应于输出控制信号和第一输出控制时钟信号缓冲内部数据而输出数据。

公开(公告)号：US07498853B2

公开(公告)日：2009-03-03

申请号：US11668023

申请日：2007-01-29

Applicant: Seong-jin Jang

Inventor： Seong-jin Jang

IPC: H03K3/00

CPC classification number: H04L25/0264

Abstract: Circuits, methods and systems are provided to reduce skew between a first digital signal that is transmitted by a first driver circuit over a first signal line, and a second digital signal that is transmitted by a second driver circuit over a second signal line. Skew may be reduced by sourcing or sinking additional current to or from the first signal line in response to the first digital signal and the second digital signal transitioning to opposite logical values, and otherwise refraining from sourcing or sinking the additional current to or from the first signal line. Skew may also be reduced between the first digital signal that is transmitted by the first driver circuit over the first signal line and a third digital signal that is transmitted by a third driver circuit over a third signal line by sourcing or sinking additional current to or from the first signal line in response to the first digital signal and the third digital signal transitioning to opposite logical values, and to otherwise refrain from sourcing or sinking the additional current to or from the first signal line.

Abstract translation: 提供了电路，方法和系统，以减少在第一信号线上由第一驱动电路传输的第一数字信号与由第二驱动电路在第二信号线上传输的第二数字信号之间的偏差。 响应于第一数字信号和第二数字信号转换到相反的逻辑值，可以通过向第一信号线或从第一信号线流出或吸收附加电流来减少倾斜，并且否则避免将附加电流从或从第一 信号线。 在第一信号线上由第一驱动电路发送的第一数字信号与第三数字信号之间的倾斜也可以减小，第三数字信号由第三驱动电路在第三信号线上传输， 所述第一信号线响应于所述第一数字信号和所述第三数字信号转变为相反的逻辑值，并且否则避免向或从所述第一信号线发出或吸收所述附加电流。

公开(公告)号：US07408482B2

公开(公告)日：2008-08-05

申请号：US11266581

申请日：2005-11-03

Applicant: Min-sang Park ,  Jin-seok Kwak ,  Seong-jin Jang

Inventor： Min-sang Park ,  Jin-seok Kwak ,  Seong-jin Jang

IPC: H03M5/00

CPC classification number: H03K19/00346

Abstract: Integrated circuit devices include data inversion circuits therein that are configured to evaluate at least first and second ordered groups of input data in parallel with an ordered group of output data previously generated by the data inversion circuit. The data inversion circuit is further configured to generate inverted versions of the first and second ordered groups of input data as versions of the first and second ordered groups of data in parallel at outputs thereof whenever a number of bit differences between the first ordered group of input data and the ordered group of output data is greater than one-half a size of the first ordered group of input data and a number of bit differences between the second ordered group of input data and the version of the first ordered group of input data is greater than one-half a size of the second ordered group of input data, respectively.

Abstract translation: 集成电路装置包括其中的数据反转电路，其被配置为与由数据反相电路预先产生的有序输出数据组并行地评估至少第一和第二有序输入数据组。 数据反转电路还被配置为当输入的第一和第二有序组数据的第一有序组合的数量与第一有序数组组的输入 数据和有序的输出数据组大于输入数据的第一个有序组的大小的一半，输入数据的第二个有序组与输入数据的第一个有序组的版本之间的位数差异为 分别大于二阶输入数据组的二分之一。

公开(公告)号：US20080056019A1

公开(公告)日：2008-03-06

申请号：US11896788

申请日：2007-09-06

Applicant: Hyun-jin Kim ,  Ho-young Song ,  Seong-jin Jang ,  Youn-sik Park

Inventor： Hyun-jin Kim ,  Ho-young Song ,  Seong-jin Jang ,  Youn-sik Park

IPC: G11C7/10 ,  G11C8/00

CPC classification number: G11C7/22 ,  G11C7/222

Abstract: A latency signal generator and method thereof are provided. The example latency signal generator may include a sampling clock signal generator adjusting a plurality of initial sampling clock signals based on a received clock signal to generate a plurality of adjusted sampling clock signals, a latch enable signal supply unit adjusting a plurality of initial latch enable signals based on a given one of the plurality of initial sampling clock signals to generate a plurality of adjusted latch enable signals and a latch unit including a plurality of latency latches, each of the plurality of latency latches selectively latching a given internal read command based on one of the plurality of adjusted sampling clock signals and one of the plurality of adjusted latch enable signals.

Abstract translation: 提供了一种等待时间信号发生器及其方法。 示例性延迟信号发生器可以包括采样时钟信号发生器，其基于所接收的时钟信号来调整多个初始采样时钟信号，以产生多个经调整的采样时钟信号;锁存使能信号供应单元，调整多个初始锁存使能信号 基于所述多个初始采样时钟信号中的给定一个以产生多个调整的锁存使能信号，以及包括多个延迟锁存器的锁存单元，所述多个延迟锁存器中的每一个基于一个等待锁存器选择性地锁存给定的内部读取命令 多个经调整的采样时钟信号中的一个和多个调整的锁存使能信号中的一个。

公开(公告)号：US20050152209A1

公开(公告)日：2005-07-14

申请号：US11011549

申请日：2004-12-14

Applicant: Won-hwa Shin ,  Seong-jin Jang ,  Sang-joon Hwang

Inventor： Won-hwa Shin ,  Seong-jin Jang ,  Sang-joon Hwang

IPC: G11C7/10 ,  G11C8/00 ,  G11C11/4093

CPC classification number: G11C7/1078 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1087 ,  G11C7/109 ,  G11C11/4093

Abstract: A synchronous semiconductor memory device includes a data input buffer and a data strobe input buffer. The data strobe input buffer includes an input buffer circuit and a detection circuit. The input buffer circuit is configured to be enabled based on an active signal, and to compare a data strobe signal with a first reference voltage to generate an internal data strobe signal. The detection circuit is configured to be enabled based on the active signal, and to compare the data strobe signal with a second reference voltage to generate a detection signal for enabling the data input buffer.

Abstract translation: 同步半导体存储器件包括数据输入缓冲器和数据选通输入缓冲器。 数据选通输入缓冲器包括输入缓冲电路和检测电路。 输入缓冲器电路被配置为基于有效信号使能，并且将数据选通信号与第一参考电压进行比较以产生内部数据选通信号。 检测电路被配置为基于有效信号使能，并且将数据选通信号与第二参考电压进行比较，以产生用于启用数据输入缓冲器的检测信号。

公开(公告)号：US09269457B2

公开(公告)日：2016-02-23

申请号：US13777428

申请日：2013-02-26

Applicant: Jeong-kyoum Kim ,  Seok-hun Hyun ,  Jung-hwan Choi ,  Seong-jin Jang

Inventor： Jeong-kyoum Kim ,  Seok-hun Hyun ,  Jung-hwan Choi ,  Seong-jin Jang

IPC: G11C29/00 ,  G11C29/04 ,  G11C29/44 ,  G11C5/04 ,  G11C11/40

CPC classification number: G11C17/18 ,  G11C5/04 ,  G11C11/40 ,  G11C17/16 ,  G11C29/04 ,  G11C29/44 ,  G11C29/76 ,  G11C29/78 ,  G11C29/789 ,  G11C2029/4402

Abstract: A memory device capable of rescuing defective characteristics that occur after packaging includes a memory cell array including a plurality of memory cells and an antifuse circuit unit including at least one antifuse. The antifuse circuit unit stores a defective cell address of the memory cell array in the at least one antifuse and reads the defective cell address to an external source. The antifuse circuit unit stores a defective characteristic code in the at least one antifuse, wherein the defective characteristic code is related to at least one of a timing parameter spec., a refresh spec., an input/output (I/O) trigger voltage spec., and a data training spec. of the memory device, and outputs the defective characteristic code to an external source.

公开(公告)号：US08891324B2

公开(公告)日：2014-11-18

申请号：US13915338

申请日：2013-06-11

Applicant: Chul-woo Yi ,  Seong-jin Jang ,  Jin-seok Kwak ,  Tai-young Ko ,  Joung-yeal Kim ,  Sang-yun Kim ,  Sang-kyun Park ,  Jung-bae Lee

Inventor： Chul-woo Yi ,  Seong-jin Jang ,  Jin-seok Kwak ,  Tai-young Ko ,  Joung-yeal Kim ,  Sang-yun Kim ,  Sang-kyun Park ,  Jung-bae Lee

IPC: G11C7/00 ,  G11C5/06 ,  G11C7/06 ,  H01L27/02 ,  H01L27/105 ,  G11C7/18 ,  G11C11/4091 ,  H01L27/108

CPC classification number: G11C5/063 ,  G11C7/062 ,  G11C7/065 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10885 ,  H01L27/10897 ,  Y10T29/41

Abstract: A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.

Abstract translation: 一种具有开放位线存储器结构的半导体存储器件，其中除去边缘伪存储器块，所述半导体存储器件包括存储器块，边沿读出放大块，其包括第一读出放大器，所述第一读出放大器具有第一位线，第一互补位线和 第一放大电路，包括具有第一尺寸的第一晶体管，中央读出放大块，包括具有第二位线的第二读出放大器，第二互补位线和第二放大电路，所述第二放大电路包括第二晶体管， 电容器块电连接到边缘检测放大块。

公开(公告)号：US20080130811A1

公开(公告)日：2008-06-05

申请号：US12029518

申请日：2008-02-12

Applicant: Seung-Jun Bae ,  Kwang-Il Park ,  Seong-jin Jang

Inventor： Seung-Jun Bae ,  Kwang-Il Park ,  Seong-jin Jang

IPC: H04L7/00 ,  G11B20/20

CPC classification number: G11C7/22 ,  G11C5/063 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222

Abstract: A data transmission/reception system can lessen a skew between data and clock signal by substantially reducing a data reception error. The data transmission/reception system using a first clock signal and a second clock signal having a phase difference corresponding to a half of data bit period as compared with the first clock signal includes a skew information extracting unit and a timing control unit. The skew information extracting unit obtains and outputs skew edge information data necessary for a skew removal by sampling data transmitted in a training operating mode as one of the first and second clock signals in a receiving side. The timing control unit receives the skew edge information data through a transmitting side, and compares its phase with a phase of the transmitted data and controls a timing between transmission data and a transmission sampling clock signal applied to a transmission output unit according to the phase comparison result. Time taken in a training operation can be relatively shortened, and circuits of the receiving side can be simplified and power consumption can be relatively reduced.

Abstract translation: 数据发送/接收系统可以通过大幅减少数据接收错误来减少数据和时钟信号之间的偏差。 使用第一时钟信号的数据发送/接收系统和与第一时钟信号相比具有对应于数据位周期的一半的相位差的第二时钟信号包括偏斜信息提取单元和定时控制单元。 偏斜信息提取单元通过在接收侧中作为第一和第二时钟信号之一的训练操作模式中发送的数据采样数据获得并输出偏斜去除所需的倾斜边缘信息数据。 定时控制单元通过发送端接收偏斜边信息数据，并将其相位与发送数据的相位进行比较，并根据相位比较控制发送数据与施加到发送输出单元的发送采样时钟信号之间的定时 结果。 可以相对缩短训练中所花费的时间，并且可以简化接收侧的电路，并且能够相对减少功耗。

公开(公告)号：US07206876B2

公开(公告)日：2007-04-17

申请号：US10734636

申请日：2003-12-15

Applicant: Seong-jin Jang

Inventor： Seong-jin Jang

IPC: G06F13/30 ,  H03K19/00

CPC classification number: H03M7/06

Abstract: An integrated circuit includes M first terminals and N second terminals, where M and N are positive integers, and where M>N>1. The circuit further includes a converter which receives M base-A-level input signals from the M first terminals, respectively, encodes each of AM values represented by the M base-A-level input signals as a different base-K value represented by N base-K-level output signals, A and K are positive integers, and where K>A>1. The converter then outputs the N base-K-level output signals to the N second terminals, respectively.

Abstract translation: 集成电路包括M个第一端子和N个第二端子，其中M和N是正整数，并且其中M> N> 1。 该电路还包括转换器，其分别从M个第一端子接收M个基本A电平输入信号，将由M个基本A电平输入信号表示的每个A-M值编码为 由N个基极K电平输出信号表示的不同的基极K值，A和K是正整数，其中K> A> 1。 然后，转换器分别将N个基本K电平输出信号输出到N个第二端子。