公开(公告)号：US20080246092A1

公开(公告)日：2008-10-09

申请号：US12072445

申请日：2008-02-26

Applicant: Seung-hwan Lee ,  Heon-jong Shin ,  Shigenobu Maeda ,  Sung-rey Wi ,  WangXiao Quan ,  Hyun-Min Choi

Inventor： Seung-hwan Lee ,  Heon-jong Shin ,  Shigenobu Maeda ,  Sung-rey Wi ,  WangXiao Quan ,  Hyun-Min Choi

IPC: H01L29/00 ,  H01L21/8238

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0207 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833

Abstract: A semiconductor device with a strain layer and a method of fabricating the semiconductor device with a strain layer that can reduce a loading effect are provided. By arranging active dummies and gate dummies not to overlap each other, the area of active dummy on which a strain layer dummy will be formed can be secured, thereby reducing the loading effect.

Abstract translation: 提供了具有应变层的半导体器件和制造具有能够减小负载效应的应变层的半导体器件的方法。 通过设置不重叠的活动假人和门虚拟物，可以确保将形成应变层虚拟物的活动虚拟物的面积，从而降低装载效果。

公开(公告)号：US07316954B2

公开(公告)日：2008-01-08

申请号：US10968233

申请日：2004-10-19

Applicant: Sang-jeong Oh ,  Yeong-kwan Kim ,  Seung-hwan Lee ,  Dong-chan Kim ,  Young-wook Park

Inventor： Sang-jeong Oh ,  Yeong-kwan Kim ,  Seung-hwan Lee ,  Dong-chan Kim ,  Young-wook Park

IPC: H01L21/8242 ,  H01L21/20

CPC classification number: H01L27/10855 ,  H01L21/28525 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/485 ,  H01L28/60 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides integrated circuit devices that include a semiconductor substrate having a semiconductor region of first conductivity type therein extending adjacent the surface of the substrate. The device further includes an electrically insulating layer with a contact hole in it that exposes the semiconductor region of first conductivity type on the surface of the semiconductor substrate. The device still further includes a poly-Si1-xGex conductive plug of first conductivity type that extends in the contact hole and is electrically connected to the semiconductor region of first conductivity type is provided. Related methods of fabricating integrated circuit devices are also provided.

Abstract translation: 本发明提供了一种集成电路器件，其包括半导体衬底，该半导体衬底具有第一导电类型的半导体区域，该半导体区域在衬底的表面附近延伸。 该器件还包括其中具有接触孔的电绝缘层，其在半导体衬底的表面上暴露出第一导电类型的半导体区域。 该器件还包括在接触孔中延伸并且电连接到第一导电类型的半导体区域的第一导电类型的多晶Si-1-x-Ge 提供导电类型。 还提供了制造集成电路器件的相关方法。

公开(公告)号：US07144771B2

公开(公告)日：2006-12-05

申请号：US10616056

申请日：2003-07-09

Applicant: Gab-jin Nam ,  Seung-hwan Lee ,  Ki-chul Kim ,  Jae-soon Lim ,  Sung-tae Kim ,  Young-sun Kim

Inventor： Gab-jin Nam ,  Seung-hwan Lee ,  Ki-chul Kim ,  Jae-soon Lim ,  Sung-tae Kim ,  Young-sun Kim

IPC: H01L21/8242

CPC classification number: H01L21/02186 ,  C23C16/405 ,  H01L21/02183 ,  H01L21/02194 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: Methods of forming an electronic device include providing a fist electrode, providing a dielectric oxide layer on the first electrode, and providing a second electrode on the dielectric oxide layer so that the dielectric oxide layer is between the first and second electrodes. More particularly, a first portion of the dielectric oxide layer adjacent the first electrode can have a first density of titanium, and a second portion of the dielectric oxide layer opposite the first electrode can have a second density of titanium different than the first density. Related structures are also discussed.

Abstract translation: 形成电子器件的方法包括提供第一电极，在第一电极上提供电介质氧化物层，并在电介质氧化物层上提供第二电极，使得电介质氧化物层位于第一和第二电极之间。 更具体地，与第一电极相邻的电介质氧化物层的第一部分可以具有第一密度的钛，并且与第一电极相对的电介质氧化物层的第二部分可具有不同于第一密度的钛的第二密度。 还讨论了相关结构。

公开(公告)号：US6077573A

公开(公告)日：2000-06-20

申请号：US83350

申请日：1998-05-22

Applicant: Young-sun Kim ,  Sang-hyeop Lee ,  Seung-hwan Lee ,  Young-wook Park ,  Mikio Takagi

Inventor： Young-sun Kim ,  Sang-hyeop Lee ,  Seung-hwan Lee ,  Young-wook Park ,  Mikio Takagi

IPC: H01L27/04 ,  C23C16/24 ,  H01L21/205 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H05H1/24

CPC classification number: C23C16/24

Abstract: A method of forming a microelectronic device includes the step of forming an impurity doped amorphous silicon layer on a microelectronic substrate using plasma-enhanced chemical vapor deposition. The impurity doped amorphous silicon layer is patterned so that portions of the microelectronic substrate are exposed adjacent the patterned amorphous silicon layer. A hemispherical grained silicon layer is then formed on the patterned amorphous silicon layer. Moreover, the step of forming the impurity doped amorphous silicon layer can be performed at a temperature of 400.degree. C. or less.

Abstract translation: 形成微电子器件的方法包括使用等离子体增强化学气相沉积在微电子衬底上形成掺杂杂质的非晶硅层的步骤。 图案化杂质掺杂非晶硅层，使得微电子衬底的部分暴露在图案化的非晶硅层附近。 然后在图案化的非晶硅层上形成半球形的硅层。 此外，形成杂质掺杂非晶硅层的步骤可以在400℃以下的温度下进行。

公开(公告)号：US08599273B2

公开(公告)日：2013-12-03

申请号：US12710495

申请日：2010-02-23

Applicant: Seung-hwan Lee

Inventor： Seung-hwan Lee

IPC: H04N5/228

CPC classification number: H04N5/23287 ,  G03B5/00

Abstract: Disclosed is a handshake correction apparatus of a photographing apparatus. The handshake correction apparatus includes a lens support plate that supports a correction lens and operates in a direction perpendicular to an optical axis; a base that supports the lens support plate to be movable; and magnets and driving coils which are assembled on the lens support plate and the base to face each other, wherein the magnets are tight-fitted in assembly grooves of the lens support plate or the base, and wherein one or more protrusions that protrude from internal walls of the assembly grooves toward the magnets and elastically press the magnets are formed in the assembly grooves. Control performance of a correction operation of the handshake correction apparatus may be improved by ensuring alignment between assembly structures of assembly parts including magnets and yokes.

Abstract translation: 公开了一种拍摄装置的握手校正装置。 握手校正装置包括支撑校正透镜并在垂直于光轴的方向上操作的透镜支撑板; 支撑透镜支撑板可移动的基座; 以及组装在透镜支撑板和基座上以彼此面对的磁体和驱动线圈，其中磁体紧密地配合在透镜支撑板或基座的组装槽中，并且其中一个或多个从内部突出的突起 在组装槽中形成朝向磁体的组装槽的壁并且弹性地挤压磁体。 可以通过确保包括磁体和轭的组装部件的组装结构之间的对准来改善握手校正装置的校正操作的控制性能。

公开(公告)号：US20110199696A1

公开(公告)日：2011-08-18

申请号：US13005096

申请日：2011-01-12

Applicant: Seung-hwan Lee ,  Jin-gi Lee ,  Jung-ho Park

Inventor： Seung-hwan Lee ,  Jin-gi Lee ,  Jung-ho Park

IPC: G02B7/04 ,  H02N2/04

CPC classification number: G02B7/08 ,  H02N2/001 ,  H02N2/026

Abstract: An optical system includes a housing, a lens assembly, and a piezoelectric actuator assembly. The lens assembly includes a lens unit having at least one lens, and a lens frame that supports the lens unit and moves in the housing. The piezoelectric actuator assembly includes a base plate coupled to the housing, an elastic plate coupled to the base plate and including a protrusion protruding from a first surface of the elastic plate, a piezoelectric element coupled to a second surface of the elastic plate wherein the piezoelectric element vibrates when receiving electricity and transmits the vibration to the elastic plate, and a moving portion that supports the lens frame. The moving portion has a first end supported by the protrusion of the elastic plate and a second end slidably coupled to the base plate.

Abstract translation: 光学系统包括壳体，透镜组件和压电致动器组件。 透镜组件包括具有至少一个透镜的透镜单元和支撑透镜单元并在壳体中移动的透镜框。 压电致动器组件包括联接到壳体的基板，耦合到基板并包括从弹性板的第一表面突出的突起的弹性板，耦合到弹性板的第二表面的压电元件，其中压电 当接收电力时元件振动并将振动传递到弹性板，以及支撑透镜框架的移动部分。 移动部分具有由弹性板的突起支撑的第一端和可滑动地联接到基板的第二端。

公开(公告)号：US20080076224A1

公开(公告)日：2008-03-27

申请号：US11756427

申请日：2007-05-31

Applicant: Min-kyung Ryu ,  Han-mei Choi ,  Seung-hwan Lee ,  Sun-jung Kim ,  Se-hoon Oh

Inventor： Min-kyung Ryu ,  Han-mei Choi ,  Seung-hwan Lee ,  Sun-jung Kim ,  Se-hoon Oh

IPC: H01L21/336

CPC classification number: H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/28282 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78 ,  H01L29/792

Abstract: A method of forming a flash memory device can include forming a tunneling oxide film on a semiconductor substrate, forming a charge storing layer on the tunneling oxide film, forming a first blocking oxide film on the charge storing layer at a first temperature, forming a second blocking oxide film on the first blocking oxide film at a second temperature higher than the first temperature, and forming a gate electrode on the second blocking oxide film.

Abstract translation: 形成闪速存储器件的方法可以包括在半导体衬底上形成隧穿氧化膜，在隧道氧化膜上形成电荷存储层，在第一温度下在电荷存储层上形成第一阻挡氧化膜，形成第二 在高于第一温度的第二温度下在第一阻挡氧化膜上形成阻挡氧化膜，以及在第二阻挡氧化膜上形成栅电极。

公开(公告)号：US07179704B2

公开(公告)日：2007-02-20

申请号：US11002571

申请日：2004-12-02

Applicant: Seung-hwan Lee ,  Jae-dong Byun ,  Sung-tae Kim ,  Young-sun Kim ,  Dal-won Lee ,  Song-won Ko

Inventor： Seung-hwan Lee ,  Jae-dong Byun ,  Sung-tae Kim ,  Young-sun Kim ,  Dal-won Lee ,  Song-won Ko

IPC: H01L21/8242

CPC classification number: H01L28/56

Abstract: Methods of forming a capacitor of a semiconductor device can include forming a lower electrode of a capacitor on a semiconductor substrate and forming a dielectric material layer of Ba(Ti1-xSnx)O3 (BTS) or Ba(Ti1-xZrx)O3 (BTZ) on the lower electrode. An amorphous layer can be formed on the dielectric material layer. An upper electrode of the capacitor can be formed on the amorphous layer.

Abstract translation: 形成半导体器件的电容器的方法可以包括在半导体衬底上形成电容器的下电极并形成Ba（Ti 1-x Sn Sn x x）的介电材料层 3）（3）（BTS）或Ba（Ti 1-x Zr x x）O 3（BTZ） 在下电极上。 可以在介电材料层上形成非晶层。 可以在非晶层上形成电容器的上电极。

公开(公告)号：US07084041B2

公开(公告)日：2006-08-01

申请号：US10795175

申请日：2004-03-05

Applicant: Hwa-sung Rhee ,  Jae-yoon Yoo ,  Ho Lee ,  Seung-hwan Lee ,  Byou-ree Lim

Inventor： Hwa-sung Rhee ,  Jae-yoon Yoo ,  Ho Lee ,  Seung-hwan Lee ,  Byou-ree Lim

IPC: H01L21/331

CPC classification number: H01L29/66287 ,  H01L29/0804 ,  H01L29/7375 ,  H01L29/7378

Abstract: A method of manufacturing a bipolar device including pre-treatment using germane gas and a bipolar device manufactured by the same. The method includes forming a single crystalline silicon layer for a base region on a collector region; and forming a polysilicon layer for an emitter region thereon. Here, before the polysilicon layer is formed, the single crystalline silicon layer is pre-treated using germane gas. Thus, an oxide layer is removed from the single crystalline silicon layer, and a germanium layer is formed on the single crystalline silicon layer, thus preventing Si-rearrangement.

Abstract translation: 一种制造双极器件的方法，其包括使用锗烷气体的预处理和由其制造的双极器件。 该方法包括在集电区上形成用于基区的单晶硅层; 并在其上形成发射极区的多晶硅层。 这里，在形成多晶硅层之前，使用锗烷气预处理单晶硅层。 因此，从单晶硅层去除氧化物层，并且在单晶硅层上形成锗层，从而防止Si重排。

公开(公告)号：US20060163558A1

公开(公告)日：2006-07-27

申请号：US11388868

申请日：2006-03-24

Applicant: Seung-hwan Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Ho Lee ,  Jae-yoon Yoo

Inventor： Seung-hwan Lee ,  Moon-han Park ,  Hwa-sung Rhee ,  Ho Lee ,  Jae-yoon Yoo

IPC: H01L31/109

CPC classification number: H01L29/7834 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628

Abstract: In a metal-oxide semiconductor (MOS) transistor with an elevated source/drain structure and in a method of fabricating the MOS transistor with the elevated source/drain structure using a selective epitaxy growth (SEG) process, a source/drain extension junction is formed after an epi-layer is formed, thereby preventing degradation of the source/drain junction region. In addition, the source/drain extension junction is partially overlapped by a lower portion of the gate layer, since two gate spacers are formed and two elevated source/drain layers are formed in accordance with the SEG process. This mitigates the short channel effect and reduces sheet resistance in the source/drain layers and the gate layer.

Abstract translation: 在具有升高的源极/漏极结构的金属氧化物半导体（MOS）晶体管中，并且使用选择性外延生长（SEG）工艺制造具有升高的源极/漏极结构的MOS晶体管的方法中，源极/漏极延伸结是 在形成外延层之后形成，从而防止源极/漏极结区域的劣化。 此外，源极/漏极延伸结部分由栅极层的下部部分地重叠，因为形成了两个栅极间隔物，并且根据SEG工艺形成两个升高的源极/漏极层。 这减轻了短沟道效应并降低了源极/漏极层和栅极层中的薄层电阻。