公开(公告)号：US07100270B2

公开(公告)日：2006-09-05

申请号：US10670416

申请日：2003-09-25

Applicant: Shao-Pin Ru

Inventor： Shao-Pin Ru

IPC: H01C17/00

CPC classification number: H05K1/167 ,  H05K1/092 ,  H05K3/108 ,  H05K3/388 ,  H05K2203/1461 ,  Y10T29/49082 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49174 ,  Y10T29/49194 ,  Y10T29/49204

Abstract: A method of fabricating printed circuit boards integrating thick film resistor components and thin film circuit portions thereon is disclosed. This is a two-phase process, where the first phase is to create multiple thick film resistors, and the second phase is to create a thin film circuit portion on the substrate with thick film resistors in existence, involving the printing of the electrodes and the resistive coating for the thick film resistors, and the printing of a low temperature passivation layer over the resistors; and the thin film circuit is formed by titanium and copper layers over the substrate, and electroplating of interconnections to form copper plated circuit. The present fabrication process does not require drilling of holes nor electroplating of leads to the resistors, thus the whole process can be automated to a greater extent than with conventional techniques.

Abstract translation: 公开了一种制造集成厚膜电阻器部件和薄膜电路部分的印刷电路板的方法。 这是一个两相工艺，其中第一阶段是制造多个厚膜电阻器，第二阶段是在存在厚膜电阻器的基板上产生薄膜电路部分，其中包括电极的印刷和 用于厚膜电阻器的电阻涂层，以及在电阻器上印刷低温钝化层; 并且薄膜电路由衬底上的钛和铜层形成，并且互连电镀形成镀铜电路。 本制造工艺不需要钻孔或将电极电镀到电阻器上，因此与常规技术相比，整个过程可以更大程度地自动化。

公开(公告)号：US20130155629A1

公开(公告)日：2013-06-20

申请号：US13469052

申请日：2012-05-10

Applicant: Shao-Pin Ru

Inventor： Shao-Pin Ru

IPC: H05K7/00 ,  H05K3/30

CPC classification number: H01L21/50 ,  B81B7/007 ,  B81B2207/096 ,  B81C2203/0109 ,  B81C2203/019 ,  H01L23/055 ,  H01L23/10 ,  H01L23/49827 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/1461 ,  Y10T29/4913 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The invention provides a semiconductor package structure, comprising: a substrate having a first surface and a second surface; a first conductive layer plated on the first surface; a semiconductor element attached to the first conductive layer on the first surface of the substrate for electrically connecting; a second conductive layer plated on the first surface and surrounded the semiconductor element and the first conductive layer, wherein the height of the second conductive layer is higher than the first conductive layer; and a lid attached to the top of the second conductive layer for sealing the semiconductor element.

Abstract translation: 本发明提供一种半导体封装结构，包括：具有第一表面和第二表面的衬底; 电镀在第一表面上的第一导电层; 半导体元件，其附接到所述基板的所述第一表面上的所述第一导电层，用于电连接; 电镀在第一表面上并包围半导体元件和第一导电层的第二导电层，其中第二导电层的高度高于第一导电层; 以及附接到第二导电层的顶部用于密封半导体元件的盖。

公开(公告)号：US20050077611A1

公开(公告)日：2005-04-14

申请号：US10680893

申请日：2003-10-08

Applicant: Shao-Pin Ru

Inventor： Shao-Pin Ru

IPC: H01L21/44 ,  H01L21/68 ,  H01L23/053

CPC classification number: H01L21/568 ,  H01L21/6835 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/09701 ,  H01L2924/15787 ,  H01L2924/18162 ,  H01L2924/00

Abstract: A package carrier has multiple ceramic substrates and a frame with a polymid tape. The frame has multiple through holes for receiving the ceramic substrates. The ceramic substrates are packaged with chips. The frame is made of plastic so the package carrier can be easily cut to separate individual electronic devices. The present invention combines individual ceramic substrates with the plastic frame so the cutting time can be reduced and the quantity of electronic devices fabricated is increased.

公开(公告)号：US20060096780A1

公开(公告)日：2006-05-11

申请号：US11312730

申请日：2005-12-20

Applicant: Shao-Pin Ru

Inventor： Shao-Pin Ru

IPC: H05K1/16

CPC classification number: H05K1/167 ,  H05K1/092 ,  H05K3/108 ,  H05K3/388 ,  H05K2203/1461 ,  Y10T29/49082 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49174 ,  Y10T29/49194 ,  Y10T29/49204

Abstract: A method of fabricating printed circuit boards integrating thick film resistor components and thin film circuit portions thereon is disclosed. This is a two-phase process, where the first phase is to create multiple thick film resistors, and the second phase is to create a thin film circuit portion on the substrate with thick film resistors in existence, involving the printing of the electrodes and the resistive coating for the thick film resistors, and the printing of a low temperature passivation layer over the resistors; and the thin film circuit is formed by titanium and copper layers over the substrate, and electroplating of interconnections to form copper plated circuit. The present fabrication process does not require drilling of holes nor electroplating of leads to the resistors, thus the whole process can be automated to a greater extent than with conventional techniques.

Abstract translation: 公开了一种制造集成厚膜电阻器部件和薄膜电路部分的印刷电路板的方法。 这是一个两相工艺，其中第一阶段是制造多个厚膜电阻器，第二阶段是在存在厚膜电阻器的基板上产生薄膜电路部分，其中包括电极的印刷和 用于厚膜电阻器的电阻涂层，以及在电阻器上印刷低温钝化层; 并且薄膜电路由衬底上的钛和铜层形成，并且互连电镀形成镀铜电路。 本制造工艺不需要钻孔或将电极电镀到电阻器上，因此与常规技术相比，整个过程可以更大程度地自动化。

公开(公告)号：US20050050724A1

公开(公告)日：2005-03-10

申请号：US10659883

申请日：2003-09-10

Applicant: Shao-Pin Ru

Inventor： Shao-Pin Ru

IPC: H05K1/03 ,  H05K3/42 ,  H05K3/46 ,  H05K1/00 ,  H05K3/10

CPC classification number: H05K3/4605 ,  H05K1/0306 ,  H05K3/423 ,  H05K2201/0154 ,  H05K2201/09563 ,  H05K2201/096 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for fabricating high integration multi-layer DPC lines on a ceramic board is to make the high density of multi-layer metal lines with insulating layer and the fine through holes. The metal lines are able to form in the different insulating layers, so as to the density of the metal lines is high. Besides the through holes defined in the ceramic board are fine, so that the space where the metal lines formed on is larger than the normal. Thus the fine through holes are stuffed with the conductive material, so that the quantity of the inductor of the metal lines is as possible as decreasing.

Abstract translation: 在陶瓷板上制造高集成多层DPC线的方法是使具有绝缘层和细通孔的多层金属线的高密度化。 金属线能够在不同的绝缘层中形成，从而金属线的密度高。 除了在陶瓷板中限定的通孔是细的，使得形成的金属线的空间大于正常。 因此，精细的通孔填充有导电材料，使得金属线的电感器的量随着减小而可能。

公开(公告)号：US20130153016A1

公开(公告)日：2013-06-20

申请号：US13330674

申请日：2011-12-20

Applicant: Shao-Pin Ru

Inventor： Shao-Pin Ru

IPC: H01L31/0224 ,  H01L31/02 ,  H01L31/18

CPC classification number: H01L31/02008 ,  H01L31/048 ,  H01L2224/73204 ,  Y02E10/50

Abstract: The present invention provides a solar cell flip chip package structure, comprising: a substrate having a first surface, a second surface and an opening extending from the first surface to the second surface; a conducting layer disposed on the first surface of the substrate; a solar cell flip chip bonded on the conducting layer; a transparent layer attached on the second surface of the substrate; and a storage space formed between the opening extending from the first surface to the second surface, the solar cell flip chip and the transparent layer.

Abstract translation: 本发明提供了一种太阳能电池倒装芯片封装结构，包括：具有第一表面，第二表面和从第一表面延伸到第二表面的开口的基板; 设置在所述基板的第一表面上的导电层; 结合在导电层上的太阳能电池倒装芯片; 安装在所述基板的第二表面上的透明层; 以及形成在从第一表面延伸到第二表面的开口之间的存储空间，太阳能电池倒装芯片和透明层。

公开(公告)号：US20130127004A1

公开(公告)日：2013-05-23

申请号：US13485939

申请日：2012-06-01

Applicant: Shao-Pin Ru

Inventor： Shao-Pin Ru

IPC: H01L31/02

CPC classification number: H01L27/14618 ,  H01L27/14683 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An image sensor module includes a substrate, a circuit layer, a flip chip, an insulating layer, and a conducting layer. The substrate has at least one transparent area and defines a first surface and a second surface. The circuit layer is provided on the first surface of the substrate. The flip chip is connected to the circuit layer. The insulating layer substantially encases the flip chip and a part of the circuit layer, wherein the insulating layer has at least one groove at a lateral side of said insulating layer thereof each provided with a metal layer. The conducting layer is provided on a top surface of the insulating layer, wherein the conducting layer is electrically connected to the circuit layer via the metal layer.

Abstract translation: 图像传感器模块包括基板，电路层，倒装芯片，绝缘层和导电层。 衬底具有至少一个透明区域并且限定第一表面和第二表面。 电路层设置在基板的第一表面上。 倒装芯片连接到电路层。 所述绝缘层基本上包含所述倒装芯片和所述电路层的一部分，其中，所述绝缘层在其绝缘层的横向侧具有至少一个设置有金属层的沟槽。 导电层设置在绝缘层的顶表面上，其中导电层通过金属层与电路层电连接。

公开(公告)号：US20060024901A1

公开(公告)日：2006-02-02

申请号：US10909877

申请日：2004-08-02

Applicant: Shao-Pin Ru

Inventor： Shao-Pin Ru

IPC: H01L21/20 ,  H01L21/44

CPC classification number: H01L21/32051 ,  H01C17/065 ,  H01L21/76838 ,  H01L27/013 ,  H05K1/092 ,  H05K1/167 ,  H05K3/108 ,  H05K3/388 ,  H05K2201/0317 ,  H05K2201/0391

Abstract: A method for fabricating a high-frequency and high-power semiconductor module uses two stages respectively adopting a thick-film process to form resistors or elements of high impedance, and a thin film process to form precise circuit wires or elements.

Abstract translation: 高频大功率半导体模块的制造方法分别采用两层分别采用厚膜工艺形成电阻器或高阻抗元件，以及薄膜工艺以形成精确的电路线或元件。

公开(公告)号：US06903456B2

公开(公告)日：2005-06-07

申请号：US10680893

申请日：2003-10-08

Applicant: Shao-Pin Ru

Inventor： Shao-Pin Ru

IPC: H01L21/44 ,  H01L21/68 ,  H01L23/053

CPC classification number: H01L21/568 ,  H01L21/6835 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/09701 ,  H01L2924/15787 ,  H01L2924/18162 ,  H01L2924/00

Abstract: A package carrier has multiple ceramic substrates and a frame with a polymid tape. The frame has multiple through holes for receiving the ceramic substrates. The ceramic substrates are packaged with chips. The frame is made of plastic so the package carrier can be easily cut to separate individual electronic devices. The present invention combines individual ceramic substrates with the plastic frame so the cutting time can be reduced and the quantity of electronic devices fabricated is increased.

Abstract translation: 包装载体具有多个陶瓷基板和具有聚粒胶带的框架。 框架具有用于接收陶瓷基板的多个通孔。 陶瓷基板与芯片一起封装。 框架由塑料制成，因此包装托架可以容易地切割以分离各个电子设备。 本发明将单独的陶瓷基板与塑料框架结合在一起，从而可以减少切割时间并增加制造的电子装置的数量。

公开(公告)号：US20050067188A1

公开(公告)日：2005-03-31

申请号：US10670416

申请日：2003-09-25

Applicant: Shao-Pin Ru

Inventor： Shao-Pin Ru

IPC: H05K1/09 ,  H05K1/16 ,  H05K3/10 ,  H05K3/38 ,  H05K3/30

CPC classification number: H05K1/167 ,  H05K1/092 ,  H05K3/108 ,  H05K3/388 ,  H05K2203/1461 ,  Y10T29/49082 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49174 ,  Y10T29/49194 ,  Y10T29/49204

Abstract: A method of fabricating printed circuit boards integrating thick film resistor components and thin film circuit portions thereon is disclosed. This is a two-phase process, where the first phase is to create multiple thick film resistors, and the second phase is to create a thin film circuit portion on the substrate with thick film resistors in existence, involving the printing of the electrodes and the resistive coating for the thick film resistors, and the printing of a low temperature passivation layer over the resistors; and the thin film circuit is formed by titanium and copper layers over the substrate, and electroplating of interconnections to form copper plated circuit. The present fabrication process does not require drilling of holes nor electroplating of leads to the resistors, thus the whole process can be automated to a greater extent than with conventional techniques.

Abstract translation: 公开了一种制造集成厚膜电阻器部件和薄膜电路部分的印刷电路板的方法。 这是一个两相工艺，其中第一阶段是制造多个厚膜电阻器，第二阶段是在存在厚膜电阻器的基板上产生薄膜电路部分，其中包括电极的印刷和 用于厚膜电阻器的电阻涂层，以及在电阻器上印刷低温钝化层; 并且薄膜电路由衬底上的钛和铜层形成，并且互连电镀形成镀铜电路。 本制造工艺不需要钻孔或将电极电镀到电阻器上，因此与常规技术相比，整个过程可以更大程度地自动化。