公开(公告)号：US12164203B2

公开(公告)日：2024-12-10

申请号：US18070579

申请日：2022-11-29

Applicant: Sharp Display Technology Corporation

Inventor： Yuhichi Saitoh ,  Hiroaki Furukawa ,  Atsushi Hachiya ,  Hiroshi Matsukizono

IPC: G02F1/1368 ,  G02F1/1333 ,  G02F1/1339 ,  G02F1/1343 ,  G02F1/1362 ,  G09G3/36 ,  H01L27/12 ,  H01L29/786

Abstract: An active matrix substrate includes a substrate, a pixel TFT that is supported by the substrate, provided corresponding to each of a plurality of pixel areas, and includes an oxide semiconductor layer, an organic insulating layer disposed above at least the oxide semiconductor layer of the pixel TFT, and an inorganic insulating layer disposed in contact with an upper surface of the organic insulating layer on the organic insulating layer. The organic insulating layer and the inorganic insulating layer are provided with a plurality of dual-layer hole structure portions, each of the dual-layer hole structure portions includes a through-hole provided in the inorganic insulating layer and a bottomed hole provided in the organic insulating layer and positioned below the through-hole, and the through-hole is positioned on an inner side of an outer edge of the bottomed hole when viewed from a normal direction of the substrate.

公开(公告)号：US12078903B2

公开(公告)日：2024-09-03

申请号：US18237501

申请日：2023-08-24

Applicant: Sharp Display Technology Corporation

Inventor： Atsushi Hachiya ,  Hiroaki Furukawa ,  Yuhichi Saitoh

IPC: G02F1/1368 ,  G02F1/1362

CPC classification number: G02F1/13685 ,  G02F1/136286

Abstract: An active matrix substrate includes: a thin film transistor located in each pixel region; and a pixel electrode electrically coupled with the thin film transistor. The thin film transistor includes a lower gate electrode, a lower gate insulating layer, an oxide semiconductor layer, an upper gate insulating layer, and an upper gate electrode. The width of an upper gate line electrically coupled with the upper gate electrode is greater than the width of a lower gate line electrically coupled with the lower gate electrode.

公开(公告)号：US11971641B2

公开(公告)日：2024-04-30

申请号：US17978312

申请日：2022-11-01

Applicant: Sharp Display Technology Corporation

Inventor： Atsushi Hachiya ,  Hiroaki Furukawa ,  Yuhichi Saitoh ,  Kuniaki Okada

IPC: G02F1/1368 ,  G02F1/1333 ,  G02F1/1343 ,  G02F1/1362 ,  H01L27/12

CPC classification number: G02F1/1368 ,  G02F1/134309 ,  G02F1/136286 ,  H01L27/124 ,  G02F1/133345 ,  G02F1/133388 ,  G02F1/13439 ,  G02F2201/48 ,  G02F2202/105 ,  G02F2202/16

Abstract: An active matrix substrate includes a first TFT disposed in each of pixel regions, a first flattened layer covering the first TFT, and a pixel electrode provided on the first flattened layer. The first TFT includes a lower gate electrode, a lower gate insulating layer, an oxide semiconductor layer, an upper gate insulating layer, and an upper gate electrode. The active matrix substrate further includes a first connection electrode for electrically connecting a drain contact region of the oxide semiconductor layer and the pixel electrode. The first flattened layer includes a pixel contact hole formed so as to expose a part of the first connection electrode. The bottom face of the pixel contact hole at least partially overlaps, of a lower gate metal layer including a lower gate electrode and an upper gate metal layer including an upper gate electrode, at least the lower gate metal layer when viewed from the normal direction of the substrate. The first connection electrode is formed from a transparent conductive material.