公开(公告)号：US20240404485A1

公开(公告)日：2024-12-05

申请号：US18621428

申请日：2024-03-29

Applicant: Sharp Display Technology Corporation

Inventor： KAORU YAMAMOTO ,  Kohhei Tanaka ,  Keiichi Yamamoto

IPC: G09G3/36

Abstract: In a first transition period during which an operation mode transitions from a normal mode to a low power consumption mode, a source driver changes the potential of each source bus line to 0 V, a gate driver sets all gate bus lines to be in a high impedance state in a state where a gate low power source voltage VGL (a potential of a second level: for example, −7 V) is applied to all of the gate bus lines, and a power source IC sets a common electrode and a VGL line to be in a high impedance state.