公开(公告)号：US11893949B2

公开(公告)日：2024-02-06

申请号：US18144063

申请日：2023-05-05

Applicant: Sharp Display Technology Corporation

Inventor： Yasushi Sasaki ,  Yuhichiroh Murakami ,  Shuji Nishi ,  Takahiro Yamaguchi

IPC: G09G3/36

CPC classification number: G09G3/3629 ,  G09G3/3614 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0842 ,  G09G2310/0278 ,  G09G2310/0291 ,  G09G2330/021

Abstract: When binary pixel data is written to a pixel circuit, of an H-level (3V) and a L-level (0V), a voltage of the level indicating the binary pixel data is held at a first node, and a voltage of the inverted level thereof is held at a second node. The first and second nodes are connected to a third node via N-channel transistors, respectively, and first and second selection control signals are supplied to gate terminals of the transistors, respectively. Voltage levels of the first and second selection control signals are periodically switched between 5V indicating the H-level and 0V indicating the L-level in a mutually inverted manner. As a result, the voltage of the first node and the voltage of the second node are alternately selected and applied to a pixel electrode of a display element.