公开(公告)号：US20250015495A1

公开(公告)日：2025-01-09

申请号：US18742072

申请日：2024-06-13

Applicant: Sharp Display Technology Corporation

Inventor： Hideki KITAGAWA ,  Yoshimasa CHIKAMA ,  Masamitsu YAMANAKA

IPC: H01Q3/36

Abstract: A phased array antenna with high yield and excellent transmission and reception performance is provided. The phased array antenna includes a printed circuit board 10 including a plurality of first terminals, a TFT substrate 50 including a plurality of second terminals and being arranged to face the printed circuit board 10, and a plurality of conductors 30 connecting the first terminals and the second terminals, respectively. The printed circuit board includes a plurality of transmission/reception electrodes 12, and beamforming ICs 20 receiving control signals from the TFT substrate via the first terminals and adjusting phases of signals transmitted and received by transmission/reception electrodes according to the control signals. The TFT substrate includes a plurality of control circuits 80 that include TFTs and generate control signals for controlling the beamforming ICs, and a planarization multilayer 70 that covers the plurality of control circuits, wherein a terrace 70t is provided on a side face of the planarization multilayer.

公开(公告)号：US20230305201A1

公开(公告)日：2023-09-28

申请号：US18121990

申请日：2023-03-15

Applicant: Sharp Display Technology Corporation

Inventor： Yutaka SAWAYAMA ,  Yoshimasa CHIKAMA ,  Masamitsu YAMANAKA ,  Hideki KITAGAWA

IPC: G02B5/10 ,  G02F1/1335 ,  G03F7/00

CPC classification number: G02B5/10 ,  G02F1/133553 ,  G03F7/0005 ,  G02F2203/02 ,  G02B5/0808

Abstract: A reflection plate includes a substrate, an insulation film disposed on the substrate and including projection portions and recesses on an uneven surface, and a reflection film disposed on the uneven surface and having a surface that conforms to the uneven surface and reflecting light. The projection portions are arranged at intervals and are inclined with respect to a normal direction of a surface of the substrate. The recesses are between the projection portions that are adjacent to each other. The projection portions include a first projection portion, a second projection portion, and a third projection portion that are inclined in different directions.

公开(公告)号：US20250105504A1

公开(公告)日：2025-03-27

申请号：US18811970

申请日：2024-08-22

Applicant: Sharp Display Technology Corporation

Inventor： Hideki KITAGAWA ,  Yoshimasa CHIKAMA ,  Masamitsu YAMANAKA

IPC: H01Q3/36

Abstract: A phased array antenna with excellent reliability is provided. The phased array antenna includes a printed circuit board 10 including a plurality of first terminals, a TFT substrate 50 including a plurality of second terminals and being arranged to face the printed circuit board 10, and a plurality of conductors 30 connecting the first terminals and the second terminals, respectively. The printed circuit board includes a plurality of transmission/reception electrodes 12, and beamforming ICs 20 receiving control signals from the TFT substrate via the first terminals and controlling phases of signals transmitted/received by transmission/reception electrodes based on the control signals. The TFT substrate includes a plurality of control circuits 90 that include TFTs and generate control signals for controlling the beamforming ICs, and a flattening multilayer 70 that covers the plurality of control circuits, wherein the flattening multilayer 70 include a plurality of recessed portions 80 each of which has an opening on a top face.

公开(公告)号：US20230178561A1

公开(公告)日：2023-06-08

申请号：US18074551

申请日：2022-12-05

Applicant: Sharp Display Technology Corporation

Inventor： Hideki KITAGAWA ,  Yoshimasa CHIKAMA ,  Masamitsu YAMANAKA

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L27/127

Abstract: An active matrix substrate includes a substrate, a plurality of thin-film transistors, a plurality of pixel electrodes, and a first insulating layer. Each pixel electrode is formed from a transparent conducting material. Each thin-film transistor includes a gate electrode, a gate insulating layer, source and drain electrodes, and an oxide semiconductor layer. The oxide semiconductor layer includes a channel region, a source contact region, and a drain contact region. The source electrode has a stack structure including a source transparent conducting layer and a source metal layer. The drain electrode includes a drain transparent conducting layer. The drain transparent conducting layer is formed integrally with a corresponding one of the plurality of pixel electrodes.