公开(公告)号：US10012883B2

公开(公告)日：2018-07-03

申请号：US15117524

申请日：2015-02-02

Applicant: Sharp Kabushiki Kaisha

Inventor： Yohsuke Kanzaki ,  Seiji Kaneko ,  Takao Saitoh ,  Yutaka Takamaru ,  Keisuke Ide

IPC: H01L21/318 ,  G02F1/1368 ,  H01L21/02 ,  G02F1/1362 ,  H01L29/66 ,  H01L29/786 ,  H01L27/12 ,  G02F1/1333 ,  H01L29/24 ,  G02F1/1343

CPC classification number: G02F1/1368 ,  G02F1/133345 ,  G02F1/136213 ,  G02F1/136227 ,  G02F2001/134372 ,  G02F2202/02 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1262 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device (100A) includes a substrate (11); a TFT (10A) supported on the substrate, the TFT including an oxide semiconductor layer (16); an organic insulating layer (24) covering the TFT; a lower layer electrode (32) on the organic insulating layer; a dielectric layer (34) on the lower layer electrode; an upper layer electrode on the dielectric layer; and an upper layer electrode (36) including a portion opposing the lower layer electrode via the dielectric layer. The dielectric layer is a silicon nitride film having a hydrogen content of 5.33×1021 atoms/cm3 or less.

公开(公告)号：US10269831B2

公开(公告)日：2019-04-23

申请号：US15039118

申请日：2014-08-26

Applicant: Sharp Kabushiki Kaisha

Inventor： Takao Saitoh ,  Seiji Kaneko ,  Yohsuke Kanzaki ,  Yutaka Takamaru ,  Keisuke Ide ,  Takuya Matsuo ,  Shigeyasu Mori ,  Hiroshi Matsukizono

IPC: H01L27/12 ,  H01L29/04 ,  H01L29/24 ,  H01L29/786 ,  H01L29/10 ,  H01L29/12

Abstract: A semiconductor device includes, a plurality of oxide semiconductor TFTs including a first gate electrode, a first insulating layer in contact with the first gate electrode, an oxide semiconductor layer opposing the first gate electrode via the first insulating layer, a source electrode and a drain electrode which are connected with the oxide semiconductor layer, and an organic insulating layer covering only some of the plurality of oxide semiconductor TFTs, wherein the plurality of oxide semiconductor TFTs include a first TFT which is covered with the organic insulating layer and a second TFT which is not covered with the organic insulating layer, and the second TFT includes a second gate electrode opposing the oxide semiconductor layer via a second insulating layer, the second gate electrode being arranged to overlap with at least a portion of the first gate electrode with the oxide semiconductor layer interposed therebetween.

公开(公告)号：US10256346B2

公开(公告)日：2019-04-09

申请号：US15516434

申请日：2015-10-01

Applicant: Sharp Kabushiki Kaisha

Inventor： Takao Saitoh ,  Yohsuke Kanzaki ,  Yutaka Takamaru ,  Keisuke Ide ,  Seiji Kaneko

IPC: H01L29/786 ,  H01L27/12 ,  C23C16/42

Abstract: In a semiconductor device including a semiconductor layer made of an oxide semiconductor, occurrence of variance in the characteristics of TFTs is suppressed. In a manufacturing process of a semiconductor device (100) where a passivation film (17) is to be formed at an upper layer of a semiconductor layer (11) made of an oxide semiconductor, deposition conditions of the passivation film (17) are set such that the proportion of pure metal (the ratio of pure metal to all the components of the semiconductor layer (11)) at an interface of the semiconductor layer (11) to the passivation film (17) becomes higher than the proportion of pure metal in the bulk of the semiconductor layer (11).

公开(公告)号：US09690155B2

公开(公告)日：2017-06-27

申请号：US15304114

申请日：2015-04-09

Applicant: Sharp Kabushiki Kaisha

Inventor： Yutaka Takamaru ,  Seiji Kaneko ,  Takao Saitoh ,  Yohsuke Kanzaki ,  Keisuke Ide ,  Hiroshi Matsukizono

IPC: G02F1/1362 ,  G02F1/1333 ,  G02F1/1368 ,  G02F1/1343

CPC classification number: G02F1/136227 ,  G02F1/133345 ,  G02F1/134363 ,  G02F1/13439 ,  G02F1/1362 ,  G02F1/1368

Abstract: A TFT substrate (100A) of a liquid crystal display panel includes: an organic interlayer insulating layer (24) covering a TFT; a first transparent electrically-conductive layer (25) provided in the first region of a surface of the organic interlayer insulating layer (24); and an inorganic dielectric layer (26) covering the first transparent electrically-conductive layer (25) and provided in a second region of the surface of the organic interlayer insulating layer (24) which is different from the first region, the inorganic dielectric layer (26) containing SiN, wherein an arithmetic mean roughness Ra of the first region and the second region of the surface of the organic interlayer insulating layer (24) is not less than 3.45 nm and not more than 5.20 nm.

公开(公告)号：US10340390B2

公开(公告)日：2019-07-02

申请号：US15569422

申请日：2016-06-02

Applicant: Sharp Kabushiki Kaisha

Inventor： Yohsuke Kanzaki ,  Takao Saitoh ,  Yutaka Takamaru ,  Keisuke Ide ,  Seiji Kaneko

IPC: H01L27/14 ,  H01L29/786 ,  H01L29/10 ,  H01L29/24 ,  H01L29/66

Abstract: One of the upper surface and the lower surface of a semiconductor layer (7) of a thin-film transistor (101) in a semiconductor device (100) is in contact with a gate insulating layer (5), and the other is in contact with a first insulating layer (11) containing silicon oxide. The semiconductor layer (7) includes a first and second oxide semiconductor layers (7A, 7B). The first oxide semiconductor layer (7A) is arranged on a gate insulating layer side of the second oxide semiconductor layer (7B) and is in contact with the second oxide semiconductor layer. The second oxide semiconductor layer (7B) contains In and Ga and does not contain Sn. The first oxide semiconductor layer (7A) contains In, Sn, and Zn. The percentage of Zn in the first oxide semiconductor layer (7A) in the depth direction does not have a maximum value in the vicinity of a surface of the first oxide semiconductor layer adjacent to the second oxide semiconductor layer. The percentage of Sn having a metallic bonding state at the interface between the first oxide semiconductor layer and the second oxide semiconductor layer is 90% or less with respect to the total amount of Sn. A region where the percentage is 50% or more has a thickness of less than 10 nm.

公开(公告)号：US09989828B2

公开(公告)日：2018-06-05

申请号：US15504963

申请日：2015-08-17

Applicant: Sharp Kabushiki Kaisha

Inventor： Yutaka Takamaru ,  Hiroshi Matsukizono ,  Tadayoshi Miyamoto ,  Takao Saitoh ,  Yohsuke Kanzaki ,  Keisuke Ide

IPC: G02F1/136 ,  G02F1/1368 ,  G02F1/1343

CPC classification number: G02F1/1368 ,  G02F1/134363 ,  G02F1/136227 ,  G02F2001/134372 ,  G02F2201/121 ,  G02F2201/123 ,  G02F2201/40 ,  G02F2202/10 ,  H01L29/786

Abstract: A semiconductor device includes: a first substrate; a gate electrode on the first substrate; a gate insulating layer on the gate electrode; an oxide semiconductor film including a channel region disposed over the gate electrode through the gate insulating layer and lowered-resistance region contacting the channel region; a source electrode and a drain electrode on the channel region; a first insulating film covering at least the channel region and including a contact hole that exposes the lowered-resistance region; and a second insulating film having reducing characteristics and disposed above the first insulating film across the contact hole, the second insulating film contacting the lowered-resistance region inside the contact hole.