公开(公告)号：US5039875A

公开(公告)日：1991-08-13

申请号：US441997

申请日：1989-11-28

Applicant: Shuen-Chin Chang

Inventor： Shuen-Chin Chang

IPC: H03K17/22

CPC classification number: H03K17/223

Abstract: A power-on reset circuit. The reset circuit provides an automatic reset pulse immediately after power-up. The supply voltage is provided to the reset circuit. An RC filter with a variable time constant provides a "hump" waveform which is coupled to a waveform shaper. The waveform shaper converts the hump voltage output from the RC filter into a reset signal. Latching mechanisms are included to prevent refiring of the reset signal.

公开(公告)号：US07167527B1

公开(公告)日：2007-01-23

申请号：US10139047

申请日：2002-05-02

Applicant: Yong E. Park ,  Shuen-Chin Chang ,  Chiayao S. Tung

Inventor： Yong E. Park ,  Shuen-Chin Chang ,  Chiayao S. Tung

IPC: H04L27/04 ,  H04L27/12 ,  H04L27/20

CPC classification number: H04L25/4917 ,  H04L25/4923

Abstract: In one aspect, apparatus and method are provided for communicating data in the form of transmission symbols conveyed in a carrier signal, wherein each transmission symbol is from a symbol set comprising a plurality of symbols which are collectively capable of representing any combination of values for at least three bits of data, wherein each symbol of the symbol set is defined with at most one transition of signal level in the carrier signal. In another aspect, apparatus and method are provided for communicating any combination of values for at least three data bits in the form of a respective transmission symbol conveyed in a carrier signal, wherein the transmission symbol is uniquely defined by a respective combination of a signal level transition, a lack of signal level transition, a signal region, and a cross-over between signal regions in the carrier signal.

Abstract translation: 在一个方面，提供了用于以载波信号中传送的传输符号的形式传送数据的装置和方法，其中每个传输符号来自包括多个符号的符号集合，这些符号集合能够表示任何值的组合 至少三位的数据，其中符号集合的每个符号在载波信号中至多一个信号电平的转变被定义。 在另一方面，提供了装置和方法，用于传送在载波信号中传送的相应传输符号形式的至少三个数据位的值的任何组合，其中传输符号由信号电平 转换，信号电平转换不足，信号区域以及载波信号中的信号区域之间的交叉。

公开(公告)号：US06324602B1

公开(公告)日：2001-11-27

申请号：US09135986

申请日：1998-08-17

Applicant: Jawji Chen ,  Shuen-Chin Chang ,  Yong E. Park

Inventor： Jawji Chen ,  Shuen-Chin Chang ,  Yong E. Park

IPC: G06F1338

CPC classification number: H03M7/30 ,  G11C7/1006 ,  G11C11/56 ,  H03M5/02

Abstract: An advanced input/output interface is provided for an integrated circuit memory having a memory storage array accessible by signals formatted in a two-level protocol. The advanced input/output interface includes a bit compression circuit for receiving a first plurality of signals formatted in the two-level protocol and generated within the integrated circuit memory. The bit compression circuit converts the first plurality of two-level protocol signals into a first signal formatted in a multi-level protocol. A bit decompression circuit receives a second signal formatted in the multi-level protocol. The bit decompression circuit converts the second multi-level protocol signal into a second plurality of signals formatted in the two-level protocol. In one embodiment, the advanced input/output interface allows for high speed/bandwidth memory accesses while reducing the pin count and operating frequency required for operation.

Abstract translation: 为具有可通过两级协议格式化的信号访问的存储器存储阵列的集成电路存储器提供高级输入/输出接口。 高级输入/输出接口包括一个位压缩电路，用于接收以两电平协议格式化并在集成电路存储器内产生的第一组多个信号。 比特压缩电路将第一多个两级协议信号转换成以多级协议格式化的第一信号。 一个解压缩电路接收以多级协议格式化的第二信号。 比特解压缩电路将第二多级协议信号转换为以两级协议格式化的第二多个信号。 在一个实施例中，高级输入/输出接口允许高速/带宽存储器访问，同时减少了操作所需的引脚数和操作频率。

公开(公告)号：US07043657B1

公开(公告)日：2006-05-09

申请号：US10682741

申请日：2003-10-08

Applicant: Jeongsik Yang ,  Young Gon Kim ,  Chiayao S. Tung ,  Shuen-Chin Chang ,  Yong E. Park

Inventor： Jeongsik Yang ,  Young Gon Kim ,  Chiayao S. Tung ,  Shuen-Chin Chang ,  Yong E. Park

IPC: G06F1/04

CPC classification number: G06F1/10

Abstract: A synchronous bus system includes a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices. The forward direction clock segment carries a forward direction clock signal, and the reverse direction clock segment carries a reverse direction clock signal. Synchronization clock circuitry, provided in each device, receives the forward direction clock signal and the reverse direction clock signal. Using the received clock signals, the synchronization clock circuitry derives a universal synchronization clock signal which is synchronous throughout all devices. Skew correction circuitry, provided in at least a portion of the devices, corrects for skew between the universal synchronization clock signal and one or more data signals for transferring data between devices.

公开(公告)号：US06937664B1

公开(公告)日：2005-08-30

申请号：US09617592

申请日：2000-07-18

Applicant: Yong E. Park ,  Jeongsik Yang ,  Shuen-Chin Chang ,  Young Gon Kim ,  Chiayao S. Tung ,  Cindy Y. Ng

Inventor： Yong E. Park ,  Jeongsik Yang ,  Shuen-Chin Chang ,  Young Gon Kim ,  Chiayao S. Tung ,  Cindy Y. Ng

IPC: H04L25/49 ,  H04L27/00

CPC classification number: H04L25/49

Abstract: An apparatus for providing multi-symbol signaling includes a multi-symbol encoder circuit. The multi-symbol encoder circuit is operable to encode data into a plurality of symbols, each symbol uniquely defined by a signal transition and a signal region in a carrier signal. A driver circuit, coupled to the multi-symbol encoder circuit, is operable to drive the carrier signal.

Abstract translation: 一种用于提供多符号信令的装置包括多符号编码器电路。 多符号编码器电路可操作以将数据编码为多个符号，每个符号由载波信号中的信号转换和信号区域唯一地定义。 耦合到多符号编码器电路的驱动器电路可操作以驱动载波信号。

公开(公告)号：US06647506B1

公开(公告)日：2003-11-11

申请号：US09452274

申请日：1999-11-30

Applicant: Jeongsik Yang ,  Young Gon Kim ,  Chiayao S. Tung ,  Shuen-Chin Chang ,  Yong E. Park

Inventor： Jeongsik Yang ,  Young Gon Kim ,  Chiayao S. Tung ,  Shuen-Chin Chang ,  Yong E. Park

IPC: G06F104

CPC classification number: G06F1/10

Abstract: A synchronous bus system includes a clock line having a forward direction clock segment and a reverse direction clock segment connected to each of a plurality of devices. The forward direction clock segment carries a forward direction clock signal, and the reverse direction clock segment carries a reverse direction clock signal. Synchronization clock circuitry, provided in each device, receives the forward direction clock signal and the reverse direction clock signal. Using the received clock signals, the synchronization clock circuitry derives a universal synchronization clock signal which is synchronous throughout all devices. Skew correction circuitry, provided in at least a portion of the devices, corrects for skew between the universal synchronization clock signal and one or more data signals for transferring data between devices.

Abstract translation: 同步总线系统包括具有连接到多个设备中的每一个的正向时钟段和反向时钟段的时钟线。 正向时钟段承载正向时钟信号，反向时钟段承载反向时钟信号。 在每个设备中提供的同步时钟电路接收正向时钟信号和反向时钟信号。 使用接收到的时钟信号，同步时钟电路产生通用同步时钟信号，其在所有设备中是同步的。 提供在装置的至少一部分中的偏斜校正电路校正通用同步时钟信号与用于在设备之间传送数据的一个或多个数据信号之间的偏斜。

公开(公告)号：US06477592B1

公开(公告)日：2002-11-05

申请号：US09369636

申请日：1999-08-06

Applicant: Jawji Chen ,  Shuen-Chin Chang ,  Yong E. Park ,  Cindy Yuklin Ng ,  Chiayao S. Tung ,  Jeongsik Yang

Inventor： Jawji Chen ,  Shuen-Chin Chang ,  Yong E. Park ,  Cindy Yuklin Ng ,  Chiayao S. Tung ,  Jeongsik Yang

IPC: G06F1320

CPC classification number: G11C7/1057 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066

Abstract: An I/O interface circuit includes an output buffer circuit and an input buffer circuit. The output buffer circuit can receive a first stream of data elements for output from the semiconductor chip, add a separate reference element for each data element in the first stream, and generate a first data transmission signal representing the data elements of the first stream and the respective reference elements. The input buffer circuit can receive a second data transmission signal representing data elements of a second stream and respective reference elements for the data elements of the second stream, sample the second data transmission signal to obtain voltage values for each data element of the second stream and the respective reference element, and interpret the voltage value for each data element of the second stream against the voltage value for the respective reference element in order to recover the data elements of the second stream.

Abstract translation: I / O接口电路包括输出缓冲电路和输入缓冲电路。 输出缓冲器电路可以接收用于从半导体芯片输出的第一数据元素流，为第一流中的每个数据元素添加单独的参考元素，并且生成表示第一流的数据元素的第一数据传输信号和 各自的参考要素。 输入缓冲器电路可以接收表示第二流的数据元素的第二数据传输信号和用于第二流的数据元素的各个参考元件，对第二数据传输信号进行采样以获得第二流的每个数据元素的电压值，以及 相应的参考元件，并且相对于相应参考元件的电压值解释第二流的每个数据元素的电压值，以便恢复第二流的数据元素。

公开(公告)号：US5187386A

公开(公告)日：1993-02-16

申请号：US641883

申请日：1991-01-16

Applicant: Shuen-Chin Chang ,  Moon G. Kim

Inventor： Shuen-Chin Chang ,  Moon G. Kim

IPC: G05F1/618 ,  G05F3/24 ,  G11C5/14 ,  G11C11/407 ,  G11C11/409 ,  H03K17/16 ,  H03K17/30

CPC classification number: G11C5/147 ,  G05F3/24 ,  H03K17/162 ,  H03K17/302

Abstract: An intermediate Dc voltage generator providing low standby current. The present invention is a CMOS-based integrated circuit that generates a reference voltage level. The present invention accomplishes this task while also minimizing power consumption allowing application for portable computers or other battery-operated devices. The present invention replaces the second stage transistors of the prior art with transistors that have channel lengths greater than the channel lengths of the first stage transistors. This increases the turn on voltage of the second stage transistors. In addition, the channel width of the second stage transistors is less than the channel width of the first stage transistors further increasing turn on voltage. In this way, the second stage transistors are off, reducing the switching current and standby current contributed by the driver transistors at second stage, and providing intermediate level voltage references. The configuration of this invention also reduces the current drawn by the second stage of transistors by providing enough margin of threshold voltage differences at first stage and second stage transistors to keep them normally off during operation of the circuit.

Abstract translation: 提供低待机电流的中间Dc电压发生器。 本发明是产生参考电压电平的基于CMOS的集成电路。 本发明实现了这一任务，同时也降低了对便携式计算机或其他电池供电设备的应用的功耗。 本发明用具有大于第一级晶体管的沟道长度的沟道长度的晶体管代替现有技术的第二级晶体管。 这增加了第二级晶体管的导通电压。 此外，第二级晶体管的沟道宽度小于第一级晶体管的沟道宽度进一步增加导通电压。 以这种方式，第二级晶体管截止，在第二级降低由驱动晶体管贡献的开关电流和待机电流，并提供中间电平电压基准。 本发明的结构还通过在第一级和第二级晶体管提供足够的阈值电压差裕度来降低由第二级晶体管汲取的电流，以在电路工作期间使它们保持常态。

公开(公告)号：US4963771A

公开(公告)日：1990-10-16

申请号：US406721

申请日：1989-09-12

Applicant: Shuen-Chin Chang

Inventor： Shuen-Chin Chang

IPC: H03K19/003 ,  H03K19/0185

CPC classification number: H03K19/018521 ,  H03K19/00315 ,  H03K19/00384

Abstract: The present invention implements a static inverter-type TTL/CMOS level translator. The present invention utilizes a pair of transistors to suppress hot electron effects. The transistor pair limits maximum VDS to VCC-VTN at the first and second gain stages. A pair of resistors serve as a virtual VCC modulator to minimize voltage variations, stabilizing the VIL/VIH trip point. The resistors also minimize standby current so that the translator of the present invention can be used in a low standby current environment. The translator of the present invention provides faster speed, wider process margins, better reliability and lower standby current than prior art translators.

Abstract translation: 本发明实现了一种静态逆变器型TTL / CMOS电平转换器。 本发明利用一对晶体管来抑制热电子效应。 晶体管对将第一和第二增益级的最大VDS限制为VCC-VTN。 一对电阻器用作虚拟VCC调制器，以最小化电压变化，稳定VIL / VIH跳变点。 电阻器还使待机电流最小化，使得本发明的转换器可以在低待机环境中使用。 与现有技术的翻译器相比，本发明的翻译器提供了更快的速度，更宽的处理余量，更好的可靠性和更低的待机电流。