公开(公告)号：US10461964B1

公开(公告)日：2019-10-29

申请号：US16169757

申请日：2018-10-24

Applicant: Silicon Laboratories Inc.

Inventor： Alexander Cherkassky ,  Bruce P. Del Signore

IPC: H04L25/02

Abstract: A driver circuit includes two pull-up portions coupled respectively between VDD and first and second driver output nodes and two pull-down sections coupled respectively between ground and third and fourth driver output nodes. The driver circuit is configurable as an RS485 driver or a CAN driver. The active diodes in the pull-up sections are turned off when necessary to prevent unwanted reverse currents between the first and second output nodes and VDD. The active diodes in the pull-down sections are turned off when necessary to prevent unwanted reverse current between ground and the third and fourth output nodes.

公开(公告)号：US20180067154A1

公开(公告)日：2018-03-08

申请号：US15258399

申请日：2016-09-07

Applicant: Silicon Laboratories Inc.

Inventor： Alexander Cherkassky ,  Bruce P. Del Signore

IPC: G01R25/00 ,  A61B5/053 ,  A61B5/00

CPC classification number: G01R27/00 ,  A61B5/024 ,  A61B5/053 ,  A61B5/0537 ,  A61B5/0816 ,  A61B5/7235 ,  A61B5/7278 ,  A61B2562/06 ,  G01N27/04 ,  G01R25/005 ,  G01R27/02

Abstract: Embodiments of synchronous detection circuits and methods are provided for extracting magnitude and phase information from a waveform. One embodiment of a synchronous detection circuit includes a driver circuit, an analog-to-digital converter (ADC) and a controller. The driver circuit is configured to supply an input waveform at an input frequency to a load. The ADC is coupled to receive an output waveform from the load, and configured for generating four digital samples, each spaced 90° apart, for every period of the output waveform. The controller is configured for setting an oversampling rate (OSR) of the ADC, so that the ADC generates an integer number, M, of sub-samples for each digital sample generated by the ADC, where the integer number, M, of sub-samples is inversely proportional to the input frequency of the input waveform. The controller is further configured to use the digital samples generated by the ADC to extract magnitude and phase information from the output waveform.

公开(公告)号：US10120005B2

公开(公告)日：2018-11-06

申请号：US15258461

申请日：2016-09-07

Applicant: Silicon Laboratories Inc.

Inventor： Alexander Cherkassky ,  Bruce P. Del Signore

IPC: G01R27/00 ,  A61B5/053 ,  G01N27/04 ,  G01R19/00 ,  A61B5/00 ,  G01R25/00 ,  G01R27/02 ,  A61B5/024 ,  A61B5/08

Abstract: Embodiments of synchronous detection circuits and methods are provided for extracting magnitude and phase information from a waveform. One embodiment of a synchronous detection circuit includes a driver circuit, an analog-to-digital converter (ADC) and a controller. The driver circuit is configured to supply an input waveform at an input frequency to a load. The ADC is coupled to receive an output waveform from the load, and configured for generating four digital samples, each spaced 90° apart, for every period of the output waveform. The controller is configured for setting an oversampling rate (OSR) of the ADC, so that the ADC generates an integer number, M, of sub-samples for each digital sample generated by the ADC, where the integer number, M, of sub-samples is inversely proportional to the input frequency of the input waveform. The controller is further configured to use the digital samples generated by the ADC to extract magnitude and phase information from the output waveform.

公开(公告)号：US10101371B2

公开(公告)日：2018-10-16

申请号：US15258399

申请日：2016-09-07

Applicant: Silicon Laboratories Inc.

Inventor： Alexander Cherkassky ,  Bruce P. Del Signore

IPC: G01R27/00 ,  A61B5/053 ,  G01N27/04 ,  G01R25/00 ,  A61B5/00 ,  G01R27/02

Abstract: Embodiments of synchronous detection circuits and methods are provided for extracting magnitude and phase information from a waveform. One embodiment of a synchronous detection circuit includes a driver circuit, an analog-to-digital converter (ADC) and a controller. The driver circuit is configured to supply an input waveform at an input frequency to a load. The ADC is coupled to receive an output waveform from the load, and configured for generating four digital samples, each spaced 90° apart, for every period of the output waveform. The controller is configured for setting an oversampling rate (OSR) of the ADC, so that the ADC generates an integer number, M, of sub-samples for each digital sample generated by the ADC, where the integer number, M, of sub-samples is inversely proportional to the input frequency of the input waveform. The controller is further configured to use the digital samples generated by the ADC to extract magnitude and phase information from the output waveform.

公开(公告)号：US20170194854A1

公开(公告)日：2017-07-06

申请号：US14983781

申请日：2015-12-30

Applicant: Silicon Laboratories Inc.

Inventor： Alexander Cherkassky ,  Bruce Del Signore

IPC: H02M3/04

CPC classification number: H02M3/1582 ,  G05F1/56

Abstract: A DC-DC converter includes a plurality of switches configured to be in a first charging mode until current through an inductor reaches a first current threshold to thereby indicate an end of the first charging mode. Responsive to the end of the first charging mode the DC-DC converter is configured to operate in a second charging mode for a time period ΔT in which a first side of the inductor is coupled to an input voltage and a second side of the inductor is coupled to a load. Responsive to the end of the time period ΔT, the DC-DC converter operates in a discharge mode until current through the inductor reaches its minimum.

公开(公告)号：US20180067063A1

公开(公告)日：2018-03-08

申请号：US15258461

申请日：2016-09-07

Applicant: Silicon Laboratories Inc.

Inventor： Alexander Cherkassky ,  Bruce P. Del Signore

IPC: G01N27/04 ,  G01R19/00 ,  A61B5/053 ,  A61B5/00 ,  A61B5/024 ,  A61B5/08

CPC classification number: G01R27/00 ,  A61B5/0002 ,  A61B5/024 ,  A61B5/053 ,  A61B5/0537 ,  A61B5/0816 ,  A61B5/7225 ,  A61B5/7278 ,  G01N27/04 ,  G01R19/0038 ,  G01R25/005 ,  G01R27/02

Abstract: Embodiments of synchronous detection circuits and methods are provided for extracting magnitude and phase information from a waveform. One embodiment of a synchronous detection circuit includes a driver circuit, an analog-to-digital converter (ADC) and a controller. The driver circuit is configured to supply an input waveform at an input frequency to a load. The ADC is coupled to receive an output waveform from the load, and configured for generating four digital samples, each spaced 90° apart, for every period of the output waveform. The controller is configured for setting an oversampling rate (OSR) of the ADC, so that the ADC generates an integer number, M, of sub-samples for each digital sample generated by the ADC, where the integer number, M, of sub-samples is inversely proportional to the input frequency of the input waveform. The controller is further configured to use the digital samples generated by the ADC to extract magnitude and phase information from the output waveform.

公开(公告)号：US09698674B1

公开(公告)日：2017-07-04

申请号：US14983781

申请日：2015-12-30

Applicant: Silicon Laboratories Inc.

Inventor： Alexander Cherkassky ,  Bruce Del Signore

IPC: G05F1/24 ,  H02M3/04 ,  H02M3/158 ,  G05F1/56

CPC classification number: H02M3/1582 ,  G05F1/56

Abstract: A DC-DC converter includes a plurality of switches configured to be in a first charging mode until current through an inductor reaches a first current threshold to thereby indicate an end of the first charging mode. Responsive to the end of the first charging mode the DC-DC converter is configured to operate in a second charging mode for a time period ΔT in which a first side of the inductor is coupled to an input voltage and a second side of the inductor is coupled to a load. Responsive to the end of the time period ΔT, the DC-DC converter operates in a discharge mode until current through the inductor reaches its minimum.