公开(公告)号：US20190214397A1

公开(公告)日：2019-07-11

申请号：US16208072

申请日：2018-12-03

Applicant: Silicon Storage Technology, Inc.

Inventor： Leo Xing ,  Andy Liu ,  Xian Liu ,  Chunming Wang ,  Melvin Dao ,  Nhan Do

IPC: H01L27/11521 ,  H01L29/423 ,  H01L29/08 ,  H01L29/10 ,  H01L23/532

CPC classification number: H01L27/11521 ,  H01L23/53295 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42328 ,  H01L29/42336

Abstract: A pair of memory cells that includes first and second spaced apart trenches formed into the upper surface of a semiconductor substrate, and first and second floating gates disposed in the first and second trenches. First and second word line gates disposed over and insulated from a portion of the upper surface that is adjacent to the first and second floating gates respectively. A source region is formed in the substrate laterally between the first and second floating gates. First and second channel regions extend from the source region, under the first and second trenches respectively, along side walls of the first and second trenches respectively, and along portions of the upper surface disposed under the first and second word line gates respectively. The first and second trenches only contain the first and second floating gates and insulation material respectively.