公开(公告)号：US20220094345A1

公开(公告)日：2022-03-24

申请号：US17457457

申请日：2021-12-03

Applicant: Socionext Inc.

Inventor： Masanori OKINOI

IPC: H03K5/135 ,  H03K5/14

Abstract: A variable delay circuit includes at least one first delay circuit and a second delay circuit. The first delay circuit includes multiple first delay elements connected in series and is configured to output a delay signal from a first stage first delay element that is a first stage of the first delay circuit. The second delay circuit includes at least one second delay element and multiple third delay elements connected in series. The second delay circuit is configured to output a delay signal from a first stage second delay element that is a first stage of the second delay circuit. The first stage first delay element and the first stage second delay element are connected in series. A delay signal obtained by delaying an input signal received at one circuit among the first delay circuit and the second delay circuit for a predetermined time duration is output from another circuit.

公开(公告)号：US20240021253A1

公开(公告)日：2024-01-18

申请号：US18468078

申请日：2023-09-15

Applicant: Socionext Inc.

Inventor： Masanori OKINOI ,  Sachio OGAWA ,  Ryo AZUMAI ,  Kiichi HAMASAKI

IPC: G11C16/32 ,  G11C7/22 ,  H03K19/0185

CPC classification number: G11C16/32 ,  G11C7/22 ,  H03K19/0185 ,  G11C5/144

Abstract: A semiconductor integrated circuit includes a buffer which outputs a memory control signal to a terminal coupled to a memory device, a power supply control circuit which controls a supply of a power supply voltage from a power supply line to the buffer based on a power control signal, a pull-up control circuit configured to control a pull-up of the terminal based on a pull-up control signal, and a control signal generating circuit. The control signal generating circuit generates, during an output period, the power control signal to supply the power supply voltage to the buffer, and the pull-up control signal to stop the pull-up of the terminal, and generates, during an idle period, the power control signal to stop the supply of the power supply voltage to the buffer, and the pull-up control signal to perform the pull-up of the terminal.