公开(公告)号：US20160268430A1

公开(公告)日：2016-09-15

申请号：US15161994

申请日：2016-05-23

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Mariam Sadaka ,  Christophe Maleville

IPC: H01L29/78 ,  H01L21/84 ,  H01L29/165 ,  H01L27/12 ,  H01L29/08 ,  H01L29/161 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/7848 ,  H01L21/02002 ,  H01L21/22 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/76254 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785

Abstract: Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.

Abstract translation: 形成半导体结构的方法包括提供具有覆盖在掩埋氧化物层上方的应变初级半导体层的外延基底层的多层衬底。 外延基底层内的元素用于改变多层基底的第一区域内的初级半导体层中的应变状态，而不改变多层基底的第二区域内的初级半导体层中的应变状态。 形成第一多个晶体管沟道结构，每个晶体管沟道结构各自包括多层衬底的第一区域内的初级半导体层的一部分，并且形成第二多个晶体管沟道结构，每个晶体管沟道结构各自包括初级半导体层的一部分 在多层基板的第二区域内。 通过这种方法制造的半导体结构可以包括具有不同应变状态的晶体管沟道结构。

公开(公告)号：US20160087100A1

公开(公告)日：2016-03-24

申请号：US14938545

申请日：2015-11-11

Applicant: Soitec

Inventor： Bich-Yen Nguyen ,  Mariam Sadaka ,  Christophe Maleville

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/165 ,  H01L27/12

CPC classification number: H01L29/7848 ,  H01L21/02002 ,  H01L21/22 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/76254 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785

Abstract: Methods of forming a semiconductor structure include providing a multi-layer substrate having an epitaxial base layer overlying a strained primary semiconductor layer above a buried oxide layer. Elements within the epitaxial base layer are used to alter a strain state in the primary semiconductor layer within a first region of the multi-layer substrate without altering a strain state in the primary semiconductor layer within a second region of the multi-layer substrate. A first plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the first region of the multi-layer substrate, and a second plurality of transistor channel structures are formed that each comprise a portion of the primary semiconductor layer within the second region of the multi-layer substrate. Semiconductor structures fabricated by such methods may include transistor channel structures having differing strain states.

公开(公告)号：US12198983B2

公开(公告)日：2025-01-14

申请号：US17756615

申请日：2020-10-26

Applicant: Soitec

Inventor： Ionut Radu ,  Hugo Biard ,  Christophe Maleville ,  Eric Guiot ,  Didier Landru

IPC: H01L21/78 ,  C23C16/32 ,  C30B25/20 ,  C30B29/36 ,  C30B31/22 ,  C30B33/10 ,  H01L21/02

Abstract: A method of producing a composite structure comprising a thin layer of monocrystalline silicon carbide arranged on a carrier substrate of silicon carbide comprises: a) a step of provision of an initial substrate of monocrystalline silicon carbide, b) a step of epitaxial growth of a donor layer of monocrystalline silicon carbide on the initial substrate, to form a donor substrate, c) a step of ion implantation of light species into the donor layer, to form a buried brittle plane delimiting the thin layer, d) a step of formation of a carrier substrate of silicon carbide on the free surface of the donor layer, comprising a deposition at a temperature of between 400° C. and 1100° C., e) a step of separation along the buried brittle plane, to form the composite structure and the remainder of the donor substrate, and f) a step of chemical-mechanical treatment(s) of the composite structure.

公开(公告)号：US20240395603A1

公开(公告)日：2024-11-28

申请号：US18694369

申请日：2022-09-20

Applicant: Soitec

Inventor： Gweltaz Gaudin ,  Christophe Maleville ,  Sidoine Odoul ,  Ionut Radu ,  Hugo Biard

IPC: H01L21/763 ,  H01L21/762 ,  H01L29/16

Abstract: A method for manufacturing a composite structure having a layer of monocrystalline silicon carbide on a polycrystalline silicon carbide carrier substrate includes: providing an initial substrate of polycrystalline silicon carbide, having a front face and comprising grains, the average size of which is greater than 0.5 μm; forming a polycrystalline silicon carbide surface layer on the initial substrate to form the carrier substrate, the surface layer including grains having an average size of less than 500 nm and having a thickness of between 50 nm and 50 μm; preparing a free surface of the surface layer of the carrier substrate to obtain a roughness of less than 1 nm RMS; (d) a step of transferring the useful layer onto the carrier substrate, by applying molecular bonding, the surface layer located between the useful layer and the initial substrate. A carrier substrate and a composite structure are formed by the method.

公开(公告)号：US20230170264A1

公开(公告)日：2023-06-01

申请号：US17995791

申请日：2021-03-29

Applicant: Soitec

Inventor： Trong Hyunh-Bao ,  Bich-Yen Nguyen ,  Christophe Maleville

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L21/762

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/42376 ,  H01L21/76281

Abstract: A method for manufacturing a semiconductor-on-insulator (SeOI) chip comprises: a) providing a SeOI structure, b) building a plurality of isolated field effect transistors (FET) each comprising: —a preliminary gate above a channel region, the FETs from a first group having a first preliminary gate length and the FETs from a second group having a smaller second preliminary gate length, —a source region and a drain region, and —a source electrode and a drain electrode, c) removing at least the preliminary gates of the FETs from the second group, leaving access to channel regions of the FETs, d) thinning a top layer in channel regions of the FETs from the second group, the top layer in channel regions of the first group of FETs having a different thickness, and e) forming functional gates simultaneously on channel regions of the FETs whose preliminary gates were removed.

公开(公告)号：US20170084478A1

公开(公告)日：2017-03-23

申请号：US15264821

申请日：2016-09-14

Applicant: Soitec ,  Peregrine Semiconductor Corporation

Inventor： Bich-Yen Nguyen ,  Christophe Maleville ,  Sinan Goktepeli ,  Anthony Mark Miscione ,  Alain Duvallet

IPC: H01L21/763 ,  H01L23/66 ,  H01L21/762 ,  H01L21/02 ,  H01L29/04 ,  H01L29/16

CPC classification number: H01L21/763 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/7624 ,  H01L21/76254 ,  H01L23/66 ,  H01L27/13 ,  H01L29/04 ,  H01L29/16

Abstract: The invention relates to a structure for radiofrequency applications comprising: a monocrystalline substrate, a polycrystalline silicon layer directly on the monocrystalline substrate, and an active layer on the polycrystalline silicon layer intended to receive radiofrequency components. At least a first portion of the polycrystalline silicon layer extending from the interface of the polycrystalline silicon layer with the monocrystalline layer includes carbon and/or nitrogen atoms located at the grain boundaries of the polycrystalline silicon at a concentration of between 2% and 20%. A process for manufacturing such a structure includes, during deposition of at least a first portion of such a polycrystalline silicon layer located at the interface with the monocrystalline substrate, depositing carbon and/or atoms in the portion.

公开(公告)号：US20250081561A1

公开(公告)日：2025-03-06

申请号：US18952033

申请日：2024-11-19

Applicant: Soitec ,  National University of Singapore

Inventor： Bich-Yen Nguyen ,  Christophe Maleville ,  Walter Schwarzenbach ,  Gong Xiao ,  Aaron Thean ,  Chen Sun ,  Haiwen Xu

IPC: H01L29/10 ,  H01L21/02 ,  H01L21/265 ,  H01L21/84 ,  H01L27/10 ,  H01L27/12 ,  H01L29/161 ,  H01L29/78

Abstract: A method of preparing a semiconductor structure includes forming an insulating layer having a thickness between about 5 nm and about 100 nm on a substrate, and forming an active layer comprising a tensile-strained silicon over the insulating layer. At least a portion of the active layer is implanted with ions to render at least a portion of the active layer amorphous and reduce the tensile strain in the at least portion of the active layer. The method further includes thermally annealing the implanted portion of the active layer and recrystallizing such previously rendered amorphous portion of the active layer. A germanium condensation process is performed on the recrystallized portion of the active layer to form a SiGe material having a compressive strain. Also described are the semiconductor structures.

公开(公告)号：US20250015122A1

公开(公告)日：2025-01-09

申请号：US18888578

申请日：2024-09-18

Applicant: Soitec

Inventor： Walter Schwarzenbach ,  Ludovic Ecarnot ,  Damien Massy ,  Nadia Ben Mohamed ,  Nicolas Daval ,  Christophe Girard ,  Christophe Maleville

IPC: H01L27/146 ,  H01L21/265 ,  H01L21/322 ,  H01L21/762 ,  H01L31/18

Abstract: A structure for a front-side image sensor comprises a semiconductor substrate, an electrically insulating layer overlying the semiconductor substrate, and an active layer overlying the electrically insulating layer. The semiconductor substrate comprises a trapping layer, the trapping layer including cavities therein. The structure further comprises a plurality of electrically isolating trenches extending vertically through the active layer to the electrically insulating layer. The plurality of electrically isolating trenches define a plurality of pixels. Also disclosed is a structure comprises a carrier substrate, an electrically insulating layer overlying the carrier substrate and a trapping layer, and a semiconductive layer overlying the electrically insulating layer. The trapping layer comprises cavities therein. The structure further comprises a plurality of electrically isolating trenches extending vertically through the semiconductive layer to the electrically insulating layer.

公开(公告)号：US20240170284A1

公开(公告)日：2024-05-23

申请号：US18550044

申请日：2022-03-03

Applicant: Soitec

Inventor： Gweltaz Gaudin ,  Christophe Maleville ,  lonut Radu ,  Hugo Biard

IPC: H01L21/02 ,  C23C16/02 ,  C23C16/32 ,  C23C16/56 ,  H01L21/762

CPC classification number: H01L21/02529 ,  C23C16/0227 ,  C23C16/325 ,  C23C16/56 ,  H01L21/02378 ,  H01L21/02447 ,  H01L21/76254

Abstract: A method for producing a semiconductor structure, comprises: a) providing a temporary substrate made of graphite having a grain size of between 4 microns and 35 microns, a porosity of between 6 and 17%, and a coefficient of thermal expansion of between 4×10-6/° C. and 5×10-6/° C.; b) depositing, on a front face of the temporary substrate, a carrier layer made of polycrystalline silicon carbide having a thickness of between 10 microns and 200 microns, c) transferring a working layer made of monocrystalline silicon carbide to the carrier layer to form a composite structure, the transfer implementing bonding by molecular adhesion, d) forming an active layer on the working layer, e) and removing the temporary substrate to form the semiconductor structure, the structure including the active layer, the working layer and the carrier layer. A composite structure is obtained in an intermediate step of the production method.

公开(公告)号：US20230260841A1

公开(公告)日：2023-08-17

申请号：US17756615

申请日：2020-10-26

Applicant: Soitec

Inventor： Ionut Radu ,  Hugo Biard ,  Christophe Maleville ,  Eric Guiot ,  Didier Landru

IPC: H01L21/78 ,  H01L21/02 ,  C30B29/36 ,  C30B25/20 ,  C30B31/22 ,  C30B33/10 ,  C23C16/32

CPC classification number: H01L21/7813 ,  H01L21/02079 ,  H01L21/02378 ,  H01L21/02447 ,  H01L21/02529 ,  H01L21/0262 ,  H01L21/02628 ,  C30B29/36 ,  C30B25/20 ,  C30B31/22 ,  C30B33/10 ,  C23C16/325

Abstract: A method of producing a composite structure comprising a thin layer of monocrystalline silicon carbide arranged on a carrier substrate of silicon carbide comprises: a) a step of provision of an initial substrate of monocrystalline silicon carbide, b) a step of epitaxial growth of a donor layer of monocrystalline silicon carbide on the initial substrate, to form a donor substrate, c) a step of ion implantation of light species into the donor layer, to form a buried brittle plane delimiting the thin layer, d) a step of formation of a carrier substrate of silicon carbide on the free surface of the donor layer, comprising a deposition at a temperature of between 400° C. and 1100° C., e) a step of separation along the buried brittle plane, to form the composite structure and the remainder of the donor substrate, and f) a step of chemical-mechanical treatment(s) of the composite structure.