Abstract:
A regulator circuit comprises: a regulator output node; at least (N+1) regulator control circuits, N being an integer greater than 1; N drivers, each one of the N drivers including: a multiplexer having an input port and an output port, the input port of the multiplexer being coupled with output nodes of the at least (N+1) regulator control circuits; an adjuster circuit configured to adjust a level of a current supplied by the driver to the regulator output node; and a task controller. The task controller is configured to: set a first one of the N+1 regulator control circuits to be idle during a first cycle of a clock signal; and set a second one of the N+1 regulator control circuits to be idle during a second cycle of the clock signal.
Abstract:
A power converter includes a first load terminal used to supply a current to a load and a second load terminal used to return a feedback voltage based on the current. A calibration circuit supplies a calibrated voltage processed from the feedback voltage, and a hysteretic comparator controls a current level of the current based on a difference between the feedback voltage and the calibrated voltage.
Abstract:
In a method, a high voltage level is converted to a low voltage level by using a high side driver and a low side driver electrically coupled with the high side driver. The high side driver is substantially turned off upon a detection that the high side driver leaves a cutoff region of the high side driver during a tri-state mode.
Abstract:
A comparator has a first terminal, a second terminal, and an output terminal. A selection circuit is coupled to the first terminal. A calibration circuit is coupled to the output terminal and the second terminal. The comparator is configured to operate in a first mode when the selection circuit provides a first input signal to the first terminal and the calibration circuit provides a second input signal to the second terminal. The comparator is configured to operate in a second mode when the selection circuit provides a first calibration signal to the first terminal and the calibration circuit provides a second calibration signal to the second terminal based on an output signal at the output terminal. The comparator generates the output signal based on the first calibration signal and the second calibration signal.
Abstract:
Voltage reference circuits are provided. A voltage reference circuit includes a transistor, a flipped-gate transistor, a first current mirror unit, a second current mirror unit, and an output note. A gate and a drain of the flipped-gate transistor are coupled to a gate and a drain of the transistor. A bulk and a source of the flipped-gate transistor are coupled to a ground. The first current mirror unit is configured to provide a first current to the flipped-gate transistor and a mirroring current in response to a bias current. The second current mirror unit is configured to drain a second current from the first transistor in response to the mirroring current. The output node is coupled to a source of the transistor and the second current mirror unit, and configured to output a reference voltage. Size of the flipped-gate transistor is less than that of the first transistor.
Abstract:
A circuit comprises a first circuit and a second circuit. The first circuit is configured to operate at a first-circuit supply voltage value, and to generate a first reference voltage value based on a voltage rated for transistors in a second circuit. The second circuit is configured to operate at a second-circuit supply voltage value, to receive a first signal and the first reference voltage value, and to clamp an input node of the second circuit based on the first reference voltage value. The second-circuit supply voltage value is less than the first-circuit supply voltage value. The first signal is configured to swing between a low voltage value and a voltage value higher than the second-circuit supply voltage value.
Abstract:
A regulator circuit includes a regulator output node, at least (N+1) regulator control circuits, and N drivers. N is an integer greater than 1. Each one of the N drivers includes a multiplexer, a driver stage, and a pre-driver stage. The multiplexer includes an input port and an output port, where the input port of the multiplexer is coupled with output nodes of the at least (N+1) regulator control circuits. The driver stage is coupled with the regulator output node. The pre-driver stage is configured to control the driver stage based on a signal on the output port of the multiplexer.
Abstract:
In a thermal sensor. a capacitor voltage of a capacitor is compared with a reference voltage, and an output voltage is generated based on the comparison. The output voltage has a pulse density indicative of a temperature detected by the thermal sensor. The capacitor is charged or discharged using at least one of a first current signal or a second current signal based on a logic level of the output voltage. The first current signal is a temperature-independent signal, and the second current signal is a temperature-dependent signal dependent on the temperature detected by the thermal sensor. In some embodiments, a clock rate of a clock signal is varied in accordance with the detected temperature to control a timing operation for supplying the first current signal to the capacitor and/or the reference voltage is varied in accordance with the detected temperature.
Abstract:
An integrated circuit includes a first conductive path over a substrate, a coil structure over the substrate, and a ferromagnetic ring. The first conductive path is configured to generate a first time-varying magnetic field based on a first time-varying current. The coil structure is configured to generate an induced electrical potential responsive to the first time-varying magnetic field. The ferromagnetic ring includes an open portion. The first conductive path extending through the open portion of the ferromagnetic ring. The first conductive path includes a first conductive line on a first level that is below the ferromagnetic ring, a second conductive line on a second level that is above the ferromagnetic ring, and a first via on a third level that is coplanar with the ferromagnetic ring, the first via electrically coupling the first conductive line and the second conductive line together.
Abstract:
A package structure includes a first package layer, a second package layer, and a chip layer positioned between the first package layer and the second package layer. The first package layer includes an electrical signal structure electrically isolated from a first thermal conduction structure. The chip layer includes an integrated circuit (IC) chip electrically connected to the electrical signal structure, a molding material, and a through-via positioned in the molding material. The first thermal conduction structure, the through-via, and the second thermal conduction structure are configured as a low thermal resistance path from the IC chip to a surface of the second package layer opposite the chip layer.