公开(公告)号：US3679883A

公开(公告)日：1972-07-25

申请号：US3679883D

申请日：1970-11-16

Applicant: TELEFUNKEN PATENT

Inventor： STRAUB DIETER

IPC: G06F7/501 ,  G06F7/50 ,  G06F7/506 ,  G06F7/385

CPC classification number: G06F7/501

Abstract: A full adder composed essentially of six identical logic circuits each arranged to receive inputs A1, A2 . . . B1, B2... and to produce outputs C A1 + A2... + B1 + B2... and C A1 + A2... (B1 + B2...), the logic circuits being arranged to receive addend input values Xi and Yi and carry inputs Zi 1, and their complements, and being arranged in at least two groups of circuits, the first group producing an output carry signal and the second group receiving inputs from the first group and producing an output sum signal.

Abstract translation: 全加器基本上由六个相同的逻辑电路组成，每个逻辑电路被布置成接收输入A1，A2。 。 。 B1，B2 ...并产生输出C = A1 + A2 ... + B1 + B2 ...和C = A1 + A2 ...（B1 + B2 ...），逻辑电路被布置为接收 加入输入值Xi和Yi，并携带输入Zi-1及其补码，并且被布置在至少两组电路中，第一组产生输出进位信号，第二组从第一组接收输入并产生输出 和信号。

公开(公告)号：US3502900A

公开(公告)日：1970-03-24

申请号：US3502900D

申请日：1968-12-06

Applicant: TELEFUNKEN PATENT

Inventor： STRAUB DIETER

IPC: H03K19/00 ,  H03K19/08 ,  H03K19/086 ,  H03K19/173

CPC classification number: H03K19/00 ,  H03K19/08 ,  H03K19/086 ,  H03K19/1733