Patent search ap:("TEXAS INSTRUMENTS INC") AND inv:"NEAL JOSEPH H" Page 1

1.

发明授权
High speed concurrent testing of dynamic read/write memory array 失效
Title translation: 动态读/写存储器阵列的高速同时测试

公开(公告)号：US4654849B1

公开(公告)日：1999-06-22

申请号：US64665684

申请日：1984-08-31

Applicant: TEXAS INSTRUMENTS INC

Inventor： WHITE LIONEL S JR , NEAL JOSEPH H , TRAN BAO G

IPC: G11C29/26 , G11C29/00 , G06F11/22

CPC classification number: G11C29/26

2.

发明授权
Dynamic memory with improved address counter for serial modes 失效
Title translation: 具有改进的串行模式地址计数器的动态存储器

公开(公告)号：US4618947B1

公开(公告)日：1998-01-06

申请号：US63490184

申请日：1984-07-26

Applicant: TEXAS INSTRUMENTS INC

Inventor： TRAN BAO G , NEAL JOSEPH H , WHITE LIONEL S

IPC: G11C11/401 , G11C7/10 , G11C11/408 , G11C11/4096 , G11C8/00

CPC classification number: G11C11/4096 , G11C7/1045

3.

发明授权
High speed concurrent testing of dynamic read/write memory array 失效

公开(公告)号：US4868823B1

公开(公告)日：1999-07-06

申请号：US14429988

申请日：1988-01-15

Applicant: TEXAS INSTRUMENTS INC

Inventor： WHITE LIONEL S JR , NEAL JOSEPH H , TRAN BAO G

IPC: G11C29/26 , G11C29/00 , G06F11/10

CPC classification number: G11C29/26

4.

发明授权
Memory module arranged for data and parity bits 失效
Title translation: 存储器模块布置用于数据和奇偶校验位

公开(公告)号：US5228132B1

公开(公告)日：1998-12-01

申请号：US80077391

申请日：1991-11-27

Applicant: TEXAS INSTRUMENTS INC

Inventor： NEAL JOSEPH H , POTEET KENNETH A

IPC: G11C11/401 , G06F11/10 , G11C5/00 , G11C5/02 , G11C7/10 , G11C8/18 , G11C29/00 , G11C29/04 , G06F13/00 , G06F1/04 , G11C7/00

CPC classification number: G06F11/1044 , G11C5/00 , G11C5/025 , G11C7/1006 , G11C7/1021 , G11C7/1033 , G11C8/18

5.

发明授权
Memory module arranged for data and parity bits 失效

公开(公告)号：US5089993B1

公开(公告)日：1998-12-01

申请号：US41507489

申请日：1989-09-29

Applicant: TEXAS INSTRUMENTS INC

Inventor： NEAL JOSEPH H , POTEET KENNETH A

IPC: G11C11/401 , G06F11/10 , G11C5/00 , G11C5/02 , G11C7/10 , G11C8/18 , G11C29/00 , G11C29/04 , G11C5/06 , G11C11/34

CPC classification number: G06F11/1044 , G11C5/00 , G11C5/025 , G11C7/1006 , G11C7/1021 , G11C7/1033 , G11C8/18

6.

发明授权
Random access memory arranged for operating synchronously with a multiprocessor and a system including a data processor a synchronous dram a peripheral device and a system clock 失效
Title translation: 布置为与多处理器同步操作的随机存取存储器和包括数据处理器的系统同步地对外围设备和系统时钟进行同步操作

公开(公告)号：US5587954B1

公开(公告)日：1998-06-23

申请号：US32754094

申请日：1994-10-21

Applicant: TEXAS INSTRUMENTS INC

Inventor： VOGLEY WILBUR C , BALISTRERI ANTHONY M , GUTTAG KARL M , KRUEGER STEVEN D , LE DUY-LOAN T , NEAL JOSEPH H , POTEET KENNETH A , HARTIGAN JOSEPH P , NORWOOD ROGER D

IPC: G06F12/00 , G11C7/10 , G11C11/407 , G11C13/00

CPC classification number: G11C7/1006 , G11C7/1018 , G11C7/1072

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