公开(公告)号：US20170315779A1

公开(公告)日：2017-11-02

申请号：US15142047

申请日：2016-04-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Alexander TESSAROLO ,  Prasanth VISWANATHAN PILLAI ,  Venkatesh NATARAJAN

IPC: G06F7/535

CPC classification number: G06F7/535

Abstract: A processor includes a core and a plurality of registers including a first register, a second register, and a third register. The core is configured to perform a division operation that includes execution of a sign extraction instruction in which a sign of at least one of a numerator value and a denominator value is stored, a conditional subtraction instruction which divides the numerator value by the denominator value to generate a quotient value and a remainder value, and a sign assignment instruction which adjusts the sign of at least one of the quotient and remainder values. The conditional subtraction instruction is configured to cause the core to perform multiple iterations of a conditional subtraction in one execution of the conditional subtraction instruction and in one clock cycle. Others methods and apparatus are described as well.

公开(公告)号：US20240069920A1

公开(公告)日：2024-02-29

申请号：US17897016

申请日：2022-08-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： David P. FOLEY ,  Alexander TESSAROLO ,  Alan L. DAVIS

IPC: G06F9/30 ,  G06F21/54

CPC classification number: G06F9/30018 ,  G06F21/54 ,  G06F2221/034

Abstract: In an example, a system includes a processor, where the processor includes a plurality of processor registers, and where the processor is configured to execute a first instruction in a first execution context. The processor is also configured to receive a PRESERVE instruction that indicates at least one processor register among the plurality of processor registers. The processor is configured to, responsive to the PRESERVE instruction, preserve parameters in the at least one processor register and clear other processor registers in the plurality of processor registers in the first execution context. The processor is also configured to execute a second instruction in a second execution context.

公开(公告)号：US20180004485A1

公开(公告)日：2018-01-04

申请号：US15198070

申请日：2016-06-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prasanth VISWANATHAN PILLAI ,  Venkatesh NATARAJAN ,  Alexander TESSAROLO

IPC: G06F7/487

CPC classification number: G06F7/4873

Abstract: A processor (and method) includes a core that performs a floating point division through execution of various instructions. The instructions include a sign, exponent, and mantissa (SEM) separation instruction which causes the core to extract the sign, exponent and mantissa values from numerator and denominator floating point numbers. The instructions also include an unsigned mantissa division instruction which cause the core to iteratively perform a conditional subtraction operation to compute a value indicative of a mantissa of the quotient. The instructions further include a merge instruction that causes the core to generate a quotient floating point number using the extracted sign and exponent from the SEM separation instruction and the value indicative of the mantissa of the quotient.

公开(公告)号：US20150113030A1

公开(公告)日：2015-04-23

申请号：US14056111

申请日：2013-10-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prohor CHOWDHURY ,  Alexander TESSAROLO

IPC: G06F17/14

CPC classification number: G06F17/142

Abstract: A system includes a memory bank and a control unit. The control unit is configured to perform FFT computations based on Merged radix-2 butterfly calculations by performing FFT computations over N input items, and to access the memory bank for (½×log2 N)×(10×log2 N) times.

Abstract translation: 系统包括存储体和控制单元。 控制单元被配置为通过在N个输入项上执行FFT计算来执行基于合并基2蝶形计算的FFT计算，并且访问存储体（½×log2N）×（10×log2N）倍）。