公开(公告)号：US20250004100A1

公开(公告)日：2025-01-02

申请号：US18391109

申请日：2023-12-20

Applicant: Texas Instruments Incorporated

Inventor： Jasbir Singh ,  Premkumar Seetharaman ,  Sandeep Rao ,  Rashmi Sachan

IPC: G01S7/35 ,  G06F3/06

Abstract: An example device includes a memory that includes a first portion and a second portion, memory control circuitry structured to receive a first set of data associated with a first radar chirp, receive a second set of data associated with a second radar chirp, store a first subset of the first set of data in the first portion of the memory, store a first subset of the second set of data in the first portion of the memory adjacent to the first subset of the first set of data, and store a second subset of the first set of data and a second subset of the second set of data in the second portion of the memory.

公开(公告)号：US11625246B2

公开(公告)日：2023-04-11

申请号：US17400828

申请日：2021-08-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ambalametil Narayanan Naveen ,  Jasbir Singh

IPC: G06F13/24 ,  G06F9/4401 ,  G06F9/30 ,  G06F9/54 ,  G06F9/48 ,  G06F9/46

Abstract: Methods, apparatus, and systems to replace values in a device are disclosed. An example apparatus includes a processor and a replacement generator coupled to the processor and configured to detect an access, by the processor, of a first instruction at a first address in a first memory, in response to the detected access, compare the first address to a set of trigger instruction address records in a second memory, wherein the set of trigger instruction address records includes a first trigger instruction address record that is associated with a first replacement address record and a first replacement value record, and based on the first address corresponding to the first trigger instruction address record, replace a first value at a second address in a third memory specified by the first replacement address record with a second value specified by the first replacement value record.

公开(公告)号：US11971470B2

公开(公告)日：2024-04-30

申请号：US18322805

申请日：2023-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jasbir Singh

IPC: G01S13/58 ,  G01S7/35 ,  G01S13/02 ,  G01S13/931 ,  H01Q3/40

CPC classification number: G01S13/584 ,  G01S7/352 ,  G01S13/0209 ,  G01S7/356 ,  G01S13/931 ,  H01Q3/40

Abstract: A non-transitory computer-readable medium stores instructions executable by a processor to process data from a radar circuit having multiple antennas. The instructions direct the processor to iteratively access a N×M range matrix indexed by N velocity bins and M antenna combinations to obtain unique X×Y range slices of the N×M range matrix, in which X is a lesser multiple of N and Y is a lesser multiple of M; iteratively access a M×S steering matrix indexed by the M antenna combinations and S hypothesis angles to obtain unique Y×Z steering vector slices of the M×S steering matrix, in which Z is a lesser multiple of S; combine the first X×Y range slice with the first Y×Z steering vector slice to form an intermediate slice, combine each subsequently accessed X×Y range slice and corresponding Y×Z steering vector slice and add the combination to the intermediate slice until a beamforming slice is formed that incorporates data for all M antenna combinations for the particular set of X velocity bins and Z hypothesis angles. An operation is then performed on the beamforming slice.

公开(公告)号：US20210200544A1

公开(公告)日：2021-07-01

申请号：US16727598

申请日：2019-12-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ambalametil Narayanan Naveen ,  Jasbir Singh

IPC: G06F9/30 ,  G06F9/54 ,  G06F9/46 ,  G06F9/48 ,  G06F13/24

Abstract: Methods, apparatus, and systems to replace values in a device are disclosed. An example apparatus includes a processor and a replacement generator coupled to the processor and configured to detect an access, by the processor, of a first instruction at a first address in a first memory, in response to the detected access, compare the first address to a set of trigger instruction address records in a second memory, wherein the set of trigger instruction address records includes a first trigger instruction address record that is associated with a first replacement address record and a first replacement value record, and based on the first address corresponding to the first trigger instruction address record, replace a first value at a second address in a third memory specified by the first replacement address record with a second value specified by the first replacement value record.

公开(公告)号：US10818374B2

公开(公告)日：2020-10-27

申请号：US16271660

申请日：2019-02-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Prakash Narayanan ,  Nikita Naresh ,  Prathyusha Teja Inuganti ,  Rakesh Channabasappa Yaraduyathinahalli ,  Aravinda Acharya ,  Jasbir Singh ,  Naveen Ambalametil Narayanan

IPC: G11C29/38 ,  G11C17/00 ,  G11C29/00 ,  G11C11/00 ,  G11C29/10 ,  G11C29/12 ,  G11C29/04 ,  G11C29/08 ,  G11C14/00 ,  G06F12/06 ,  G06F9/4401

Abstract: A system includes a volatile storage device, a read-only memory (ROM), a memory built-in self-test (BIST) controller and a central processing unit (CPU). The CPU, upon occurrence of a reset event, executes a first instruction from the ROM to cause the CPU to copy a plurality of instructions from a range of addresses in the ROM to the volatile storage device. The CPU also executes a second instruction from the ROM to change a program counter. The CPU further executes the plurality of instructions from the volatile storage device using the program counter. The CPU, when executing the plurality of instructions from the volatile storage device, causes the ROM to enter a test mode and the memory BIST controller to be configured to test the ROM.

公开(公告)号：US09829581B2

公开(公告)日：2017-11-28

申请号：US14693497

申请日：2015-04-22

Applicant: Texas Instruments Incorporated

Inventor： Jasbir Singh ,  Jawaharlal Tangudu ,  Aravind Ganesan

IPC: G01S19/28 ,  G01S19/30 ,  G01S19/37 ,  G01S19/24 ,  G01R31/28

CPC classification number: G01S19/28 ,  G01R31/2851 ,  G01S19/24 ,  G01S19/30 ,  G01S19/37

Abstract: Enhancing search capacity of Global Navigation Satellite System (GNSS) receivers. A method for searching satellite signals in a receiver includes performing a plurality of searches sequentially. The method also includes storing a result from each search of the plurality of searches in a consecutive section of a memory. Further, the method includes detecting free sections in the memory. The method also includes concatenating the free sections in the memory to yield a concatenated free section. Moreover, the method includes allocating the concatenated free section for performing an additional search.

公开(公告)号：US20140035784A1

公开(公告)日：2014-02-06

申请号：US14047131

申请日：2013-10-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jasbir Singh ,  Jawaharlal Tangudu ,  Aravind Ganesan

IPC: G01S19/28

CPC classification number: G01S19/28 ,  G01R31/2851 ,  G01S19/24 ,  G01S19/30 ,  G01S19/37

Abstract: Enhancing search capacity of Global Navigation Satellite System (GNSS) receivers. A method for searching satellite signals in a receiver includes performing a plurality of searches sequentially. The method also includes storing a result from each search of the plurality of searches in a consecutive section of a memory. Further, the method includes detecting free sections in the memory. The method also includes concatenating the free sections in the memory to yield a concatenated free section. Moreover, the method includes allocating the concatenated free section for performing an additional search.

Abstract translation: 提高全球导航卫星系统（GNSS）接收机的搜索能力。 用于在接收机中搜索卫星信号的方法包括顺序执行多个搜索。 该方法还包括将来自多个搜索的每次搜索的结果存储在存储器的连续部分中。 此外，该方法包括检测存储器中的空闲部分。 该方法还包括连接存储器中的空闲部分以产生级联的自由部分。 此外，该方法包括分配用于执行附加搜索的级联空闲部分。

公开(公告)号：US12081362B2

公开(公告)日：2024-09-03

申请号：US17192271

申请日：2021-03-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jasbir Singh ,  Brian Ginsburg

IPC: H04L12/40 ,  G06F16/28

CPC classification number: H04L12/40117 ,  G06F16/288 ,  H04L12/40071 ,  H04L2012/40273

Abstract: A method includes receiving first data at a controller of an ADAS via a first virtual channel of a camera serial interface 2 (CSI-2) data interface. The method also includes receiving second data at the controller of the ADAS via a second virtual channel of the CSI-2 data interface. The method includes storing the first data at a first address in a memory, the first address specified by the first virtual channel. The method also includes storing the second data at a second address of a control register, the control register specified by the second data. The method includes performing a test using the first data and the second data.

公开(公告)号：US11709248B2

公开(公告)日：2023-07-25

申请号：US17094338

申请日：2020-11-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jasbir Singh

IPC: G01S13/58 ,  G01S13/02 ,  G01S7/35 ,  G01S13/931 ,  H01Q3/40

CPC classification number: G01S13/584 ,  G01S7/352 ,  G01S13/0209 ,  G01S7/356 ,  G01S13/931 ,  H01Q3/40

Abstract: A non-transitory computer-readable medium stores instructions that cause processors to obtain an N×M range matrix comprising radar data indexed by velocity and antenna and an M×S steering matrix comprising expected phases indexed by antenna and hypothesis angle. For each unique X×Y range slice corresponding to a particular set of X velocities, processors store the particular range slice in a first buffer. For each unique Y×Z steering slice corresponding to a particular set of Y antenna, processors store the particular steering slice in a second buffer. The processors perform beamforming operations on the range, steering, and intermediate slices, storing the result in a third buffer as the intermediate slice. After each steering and range slice for the particular set of X velocities has been iterated through, the processors store the intermediate slice as a beamforming slice for the particular set of X velocities and the hypothesis angles.

公开(公告)号：US11366715B2

公开(公告)日：2022-06-21

申请号：US17027888

申请日：2020-09-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Desmond Fernandes ,  Indu Prathapan ,  Jasbir Singh ,  Prathap Srinivasan ,  Rishav Karki

IPC: G06F11/10 ,  G06F13/40 ,  G06F11/07

Abstract: A device includes a first component having a data input and a data output. The deice further includes an error correction code (ECC) generation circuit having an input coupled to the data input of the first component. The ECC generation circuit has an output. A second component has a data input coupled to the output of the ECC generation circuit. The second component has a data output. An ECC error detection circuit has a first data input coupled to the data output of the first component, and a second data input coupled to the data output of the second component.