公开(公告)号：US12166071B2

公开(公告)日：2024-12-10

申请号：US17884849

申请日：2022-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ko-Cheng Liu ,  Ming-Shuan Li ,  Ming-Lung Cheng ,  Chang-Miao Liu

IPC: H01L29/06 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/092 ,  H01L29/66

Abstract: A semiconductor structure includes a power rail, a dielectric layer over the power rail, a first source/drain feature over the dielectric layer, a via structure extending through the dielectric layer and electrically connecting the first source/drain feature to the power rail, and two dielectric fins disposed on both sides of the first source/drain feature. Each of the dielectric fins includes two seal spacers, a dielectric bottom cover between bottom portions of the seal spacers, a dielectric top cover between top portions of the seal spacers, and an air gap surrounded by the seal spacers, the dielectric bottom cover, and the dielectric top cover.

公开(公告)号：US11948998B2

公开(公告)日：2024-04-02

申请号：US17815913

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Chang-Miao Liu ,  Huiling Shang

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/08 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/225 ,  H01L21/265 ,  H01L29/06

CPC classification number: H01L29/66742 ,  H01L21/7624 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66787 ,  H01L29/78603 ,  H01L29/78696 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/2253 ,  H01L21/26533 ,  H01L29/0673

Abstract: A method includes forming a semiconductor substrate having an oxide layer embedded therein, forming a multi-layer (ML) stack including alternating channel layers and non-channel layers over the semiconductor substrate, forming a dummy gate stack over the ML, forming an S/D recess in the ML to expose the oxide layer, forming an epitaxial S/D feature in the S/D recess, removing the non-channel layers from the ML to form openings between the channel layers, where the openings are formed adjacent to the epitaxial S/D feature, and forming a high-k metal gate stack (HKMG) in the openings between the channel layers and in place of the dummy gate stack.

公开(公告)号：US11855155B2

公开(公告)日：2023-12-26

申请号：US17658779

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Xusheng Wu ,  Chang-Miao Liu ,  Ying-Keung Leung ,  Huiling Shang ,  Youbo Lin

IPC: H01L29/40 ,  H01L21/768 ,  H01L21/283 ,  H01L29/45 ,  H01L21/285 ,  H01L29/66

CPC classification number: H01L29/401 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L29/456 ,  H01L29/665

Abstract: A method including providing a device including a gate structure and a source/drain feature adjacent to the gate structure. An insulating layer (e.g., CESL, ILD) is formed over the source/drain feature. A trench is etched in the insulating layer to expose a surface of the source/drain feature. A semiconductor material is then formed in the etched trench on the surface of the source/drain feature. The semiconductor material is converted to a silicide.

公开(公告)号：US11756835B2

公开(公告)日：2023-09-12

申请号：US17861679

申请日：2022-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Lun Min ,  Xusheng Wu ,  Chang-Miao Liu

IPC: H01L21/8234 ,  H01L21/764 ,  H01L27/088

CPC classification number: H01L21/823481 ,  H01L21/764 ,  H01L21/823431 ,  H01L27/0886

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a first semiconductor fin and a second semiconductor fin formed over a substrate, wherein lower portions of the first semiconductor fin and the second semiconductor fin are separated by an isolation structure; a first gate stack formed over the first semiconductor fin and a second gate stack formed over the second semiconductor fin; and a separation feature separating the first gate stack and the second gate stack, wherein the separation feature includes a first dielectric layer and a second dielectric layer with an air gap defined therebetween, and a bottom portion of the separation feature being inserted into the isolation structure.

公开(公告)号：US11594680B2

公开(公告)日：2023-02-28

申请号：US17463790

申请日：2021-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Miao Liu ,  Bwo-Ning Chen ,  Kei-Wei Chen

IPC: H01L45/00

Abstract: A method of forming a semiconductor device includes patterning a mask layer and a semiconductor material to form a first fin and a second fin with a trench interposing the first fin and the second fin. A first liner layer is formed over the first fin, the second fin, and the trench. An insulation material is formed over the first liner layer. A first anneal is performed, followed by a first planarization of the insulation material to form a first planarized insulation material. After which, a top surface of the first planarized insulation material is over a top surface of the mask layer. A second anneal is performed, followed by a second planarization of the first planarized insulation material to form a second planarized insulation material. The insulation material is etched to form shallow trench isolation (STI) regions, and a gate structure is formed over the semiconductor material.

公开(公告)号：US11133386B2

公开(公告)日：2021-09-28

申请号：US16735379

申请日：2020-01-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bwo-Ning Chen ,  Xusheng Wu ,  Chang-Miao Liu

IPC: H01L29/10 ,  H01L27/092 ,  H01L29/78 ,  H01L29/161 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/265

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The structure includes a semiconductor substrate; a fin extending above the semiconductor substrate, wherein the fin includes a first layer over the semiconductor substrate and a second layer over the first layer, wherein the first layer includes silicon germanium having a first concentration of germanium, and wherein the second layer includes silicon germanium having a second concentration of germanium less than the first concentration of germanium; and a gate stack disposed over the fin.

公开(公告)号：US20210090959A1

公开(公告)日：2021-03-25

申请号：US16899225

申请日：2020-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Lun Min ,  Chang-Miao Liu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/768 ,  H01L27/088

Abstract: A dummy gate is formed over a substrate. A sacrificial layer is formed over the dummy gate. An interlayer dielectric (ILD) is formed over the dummy gate and over the sacrificial layer. The dummy gate is replaced with a metal-containing gate. The sacrificial layer is removed. A removal of the sacrificial layer leaves air gaps around the metal-containing gate. The air gaps are then sealed.

公开(公告)号：US20240387281A1

公开(公告)日：2024-11-21

申请号：US18787051

申请日：2024-07-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Lun Min ,  Xusheng Wu ,  Chang-Miao Liu

IPC: H01L21/8234 ,  H01L21/764 ,  H01L27/088

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a first semiconductor fin and a second semiconductor fin formed over a substrate, wherein lower portions of the first semiconductor fin and the second semiconductor fin are separated by an isolation structure; a first gate stack formed over the first semiconductor fin and a second gate stack formed over the second semiconductor fin; and a separation feature separating the first gate stack and the second gate stack, wherein the separation feature includes a first dielectric layer and a second dielectric layer with an air gap defined therebetween, and a bottom portion of the separation feature being inserted into the isolation structure.

公开(公告)号：US20240379744A1

公开(公告)日：2024-11-14

申请号：US18780742

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ko-Cheng Liu ,  Ming-Shuan Li ,  Ming-Lung Cheng ,  Chang-Miao Liu

IPC: H01L29/06 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/092 ,  H01L29/66

Abstract: A semiconductor structure includes a power rail, a dielectric layer over the power rail, a first source/drain feature over the dielectric layer, a via structure extending through the dielectric layer and electrically connecting the first source/drain feature to the power rail, and two dielectric fins disposed on both sides of the first source/drain feature. Each of the dielectric fins includes two seal spacers, a dielectric bottom cover between bottom portions of the seal spacers, a dielectric top cover between top portions of the seal spacers, and an air gap surrounded by the seal spacers, the dielectric bottom cover, and the dielectric top cover.

公开(公告)号：US12113118B2

公开(公告)日：2024-10-08

申请号：US17815181

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bwo-Ning Chen ,  Xusheng Wu ,  Chang-Miao Liu ,  Shih-Hao Lin

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L29/06 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/76832 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/7848

Abstract: A method includes forming a silicon liner over a semiconductor device, which includes a dummy gate structure disposed over a substrate and S/D features disposed adjacent to the dummy gate structure, where the dummy gate structure traverses a channel region between the S/D features. The method further includes forming an ILD layer over the silicon liner, which includes elemental silicon, introducing a dopant species to the ILD layer, and subsequently removing the dummy gate structure to form a gate trench. Thereafter, the method proceeds to performing a thermal treatment to the doped ILD layer, thereby oxidizing the silicon liner, and forming a metal gate stack in the gate trench and over the oxidized silicon liner.