公开(公告)号：US20230378052A1

公开(公告)日：2023-11-23

申请号：US18365009

申请日：2023-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ming Huang ,  Ming-Da Cheng ,  Songbor Lee ,  Jung-You Chen ,  Ching-Hua Kuan ,  Tzy-Kuang Lee

IPC: H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5223 ,  H01L24/03 ,  H01L23/5226 ,  H01L28/60 ,  H01L2224/02313 ,  H01L2224/02311

Abstract: A method includes depositing a first passivation layer over a conductive feature, wherein the first passivation layer has a first dielectric constant, forming a capacitor over the first passivation layer, and depositing a second passivation layer over the capacitor, wherein the second passivation layer has a second dielectric constant greater than the first dielectric constant. The method further includes forming a redistribution line over and electrically connecting to the capacitor, depositing a third passivation layer over the redistribution line, and forming an Under-Bump-Metallurgy (UBM) penetrating through the third passivation layer to electrically connect to the redistribution line.

公开(公告)号：US12255131B2

公开(公告)日：2025-03-18

申请号：US18365009

申请日：2023-08-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ming Huang ,  Ming-Da Cheng ,  Songbor Lee ,  Jung-You Chen ,  Ching-Hua Kuan ,  Tzy-Kuang Lee

IPC: H01L23/522 ,  H01L23/00 ,  H01L49/02

Abstract: A method includes depositing a first passivation layer over a conductive feature, wherein the first passivation layer has a first dielectric constant, forming a capacitor over the first passivation layer, and depositing a second passivation layer over the capacitor, wherein the second passivation layer has a second dielectric constant greater than the first dielectric constant. The method further includes forming a redistribution line over and electrically connecting to the capacitor, depositing a third passivation layer over the redistribution line, and forming an Under-Bump-Metallurgy (UBM) penetrating through the third passivation layer to electrically connect to the redistribution line.

公开(公告)号：US11935826B2

公开(公告)日：2024-03-19

申请号：US17197483

申请日：2021-03-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ming Huang ,  Ming-Da Cheng ,  Songbor Lee ,  Jung-You Chen ,  Ching-Hua Kuan ,  Tzy-Kuang Lee

IPC: H01L23/522 ,  H01L23/00 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L23/5226 ,  H01L24/03 ,  H01L28/60 ,  H01L2224/02311 ,  H01L2224/02313

Abstract: A method includes depositing a first passivation layer over a conductive feature, wherein the first passivation layer has a first dielectric constant, forming a capacitor over the first passivation layer, and depositing a second passivation layer over the capacitor, wherein the second passivation layer has a second dielectric constant greater than the first dielectric constant. The method further includes forming a redistribution line over and electrically connecting to the capacitor, depositing a third passivation layer over the redistribution line, and forming an Under-Bump-Metallurgy (UBM) penetrating through the third passivation layer to electrically connect to the redistribution line.

公开(公告)号：US10109739B2

公开(公告)日：2018-10-23

申请号：US15099606

申请日：2016-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Hua Kuan ,  Chen-Chieh Chiang ,  Chi-Cherng Jeng

IPC: H01L29/78 ,  H01L29/06

Abstract: A FinFET including a substrate, a plurality of insulators and a gate stack is provided. The substrate comprises a plurality of trenches and at least one semiconductor fin between the trenches, wherein the semiconductor fin comprises at least one groove, and the at least one groove is located on a top surface of the semiconductor fin. The insulators are disposed in the trenches. The gate stack partially covers the semiconductor fin, the at least one groove and the insulators.

公开(公告)号：US20170301795A1

公开(公告)日：2017-10-19

申请号：US15099606

申请日：2016-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Hua Kuan ,  Chen-Chieh Chiang ,  Chi-Cherng Jeng

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/7853

Abstract: A FinFET including a substrate, a plurality of insulators and a gate stack is provided. The substrate comprises a plurality of trenches and at least one semiconductor fin between the trenches, wherein the semiconductor fin comprises at least one groove, and the at least one groove is located on a top surface of the semiconductor fin. The insulators are disposed in the trenches. The gate stack partially covers the semiconductor fin, the at least one groove and the insulators.