公开(公告)号：US20250149488A1

公开(公告)日：2025-05-08

申请号：US18585599

申请日：2024-02-23

Applicant: Taiwan Semiconductor Manufacturing Co, Ltd.

Inventor： Wei-Yu Chen ,  Chao-Wei Chiu ,  Hsin Liang Chen ,  Hao-Jan Shih ,  Hao-Jan Pei ,  Hsiu-Jen Lin

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: In an embodiment, a method includes forming a device region along a first substrate; forming an interconnect structure over the device region and the first substrate; forming a metal pillar over the interconnect structure, forming the metal pillar comprising: forming a base layer over the interconnect structure; forming an intermediate layer over the base layer; and forming a capping layer over the intermediate layer; forming a solder region over the capping layer; and performing an etch process to recess sidewalls of the base layer and the capping layer from sidewalls of the intermediate layer and the solder region.

公开(公告)号：US20240387346A1

公开(公告)日：2024-11-21

申请号：US18366255

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chiang Tsao ,  Chao-Wei Chiu ,  Hsin Liang Chen ,  Chia-Shen Cheng ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

Abstract: Embodiments include a device. The device includes an interposer, a package substrate, and conductive connectors bonding the package substrate to the interposer. Each of the conductive connectors have convex sidewalls. A first subset of the conductive connectors are disposed in a center of the package substrate in a top-down view. A second subset of the conductive connectors are disposed in an edge/corner of the package substrate in the top-down view. Each of the second subset of the conductive connectors have a greater height than each of the first subset of the conductive connectors.

公开(公告)号：US11482491B2

公开(公告)日：2022-10-25

申请号：US15877398

申请日：2018-01-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Chih-Hua Chen ,  Ching-Hua Hsieh ,  Hsiu-Jen Lin ,  Yu-Chih Huang ,  Yu-Peng Tsai ,  Chia-Shen Cheng ,  Chih-Chiang Tsao ,  Jen-Jui Yu

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/522 ,  H01L23/538 ,  H01L21/683

Abstract: A package structure includes an insulating encapsulation, at least one die, and conductive structures. The at least one die is encapsulated in the insulating encapsulation. The conductive structures are located aside of the at least one die and surrounded by the insulating encapsulation, and at least one of the conductive structures is electrically connected to the at least one die. Each of the conductive structures has a first surface, a second surface opposite to the first surface and a slant sidewall connecting the first surface and the second surface, and each of the conductive structures has a top diameter greater than a bottom diameter thereof, and wherein each of the conductive structures has a plurality of pores distributed therein.

公开(公告)号：US11049832B2

公开(公告)日：2021-06-29

申请号：US16876371

申请日：2020-05-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Jan Pei ,  Chih-Chiang Tsao ,  Wei-Yu Chen ,  Hsiu-Jen Lin ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L21/00 ,  H01L25/10 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31 ,  H01L21/683 ,  H01L25/11

Abstract: A method for forming a package structure is provided. The method includes forming a protective layer to surround a semiconductor die and forming a conductive structure over the protective layer. The method also includes disposing a polymer-containing material over the protective layer to partially surround the conductive structure. The method further includes curing the polymer-containing material to form a warpage-control element.

公开(公告)号：US12144065B2

公开(公告)日：2024-11-12

申请号：US17869384

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Hsiu-Jen Lin ,  Cheng-Ting Chen ,  Wei-Yu Chen ,  Chien-Wei Lee ,  Chung-Shi Liu

IPC: B23K3/08 ,  H01L21/677 ,  H01L21/68 ,  H01L21/683 ,  H01L23/00 ,  H05B3/02 ,  B23K101/40

Abstract: A method includes placing a first package component over a vacuum boat, wherein the vacuum boat comprises a hole, and wherein the first package component covers the hole. A second package component is placed over the first package component, wherein solder regions are disposed between the first and the second package components. The hole is vacuumed, wherein the first package component is pressed by a pressure against the vacuum boat, and wherein the pressure is generated by a vacuum in the hole. When the vacuum in the hole is maintained, the solder regions are reflowed to bond the second package component to the first package component.

公开(公告)号：US12040309B2

公开(公告)日：2024-07-16

申请号：US17815713

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Chia-Shen Cheng ,  Hao-Jan Pei ,  Philip Yu-Shuan Chung ,  Kuei-Wei Huang ,  Yu-Peng Tsai ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh ,  Chen-Hua Yu ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/49822 ,  H01L24/17 ,  H01L2224/175 ,  H01L2224/81224 ,  H01L2924/3511

Abstract: A method includes performing a first laser shot on a first portion of a top surface of a first package component. The first package component is over a second package component, and a first solder region between the first package component and the second package component is reflowed by the first laser shot. After the first laser shot, a second laser shot is performed on a second portion of the top surface of the first package component. A second solder region between the first package component and the second package component is reflowed by the second laser shot.

公开(公告)号：US20240153842A1

公开(公告)日：2024-05-09

申请号：US18404504

申请日：2024-01-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Jan Pei ,  Wei-Yu Chen ,  Chia-Shen Cheng ,  Chih-Chiang Tsao ,  Cheng-Ting Chen ,  Chia-Lun Chang ,  Chih-Wei Lin ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L23/373 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/50 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L23/3736 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/83 ,  H01L25/105 ,  H01L23/49816 ,  H01L2924/15311

Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.

公开(公告)号：US11901258B2

公开(公告)日：2024-02-13

申请号：US17227790

申请日：2021-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Jan Pei ,  Wei-Yu Chen ,  Chia-Shen Cheng ,  Chih-Chiang Tsao ,  Cheng-Ting Chen ,  Chia-Lun Chang ,  Chih-Wei Lin ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L23/373 ,  H01L23/50 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L25/10 ,  H01L23/367 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L23/3736 ,  H01L21/486 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/83 ,  H01L25/105 ,  H01L23/49816 ,  H01L2224/18 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/29099

Abstract: A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.

公开(公告)号：US20230386862A1

公开(公告)日：2023-11-30

申请号：US18447409

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Hao-Jan Pei ,  Hsuan-Ting Kuo ,  Chih-Chiang Tsao ,  Jen-Jui Yu ,  Philip Yu-Shuan Chung ,  Chia-Lun Chang ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh

IPC: H01L21/50 ,  H01L21/48 ,  H01L23/00 ,  B23K1/00 ,  H01L21/60

CPC classification number: H01L21/50 ,  H01L21/4853 ,  H01L24/10 ,  B23K1/0016 ,  H01L2021/60225 ,  H01L2021/60135

Abstract: A method includes forming regions of solder paste on a redistribution structure, wherein the solder paste has a first melting temperature; forming solder bumps on an interconnect structure, wherein the solder bumps have a second melting temperature that is greater than the first melting temperature; placing the solder bumps on the regions of solder paste; performing a first reflow process at a first reflow temperature for a first duration of time, wherein the first reflow temperature is less than the second melting temperature; and after performing the first reflow process, performing a second reflow process at a second reflow temperature for a second duration of time, wherein the second reflow temperature is greater than the second melting temperature.

公开(公告)号：US11646293B2

公开(公告)日：2023-05-09

申请号：US16935465

申请日：2020-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Shen Cheng ,  Wei-Yu Chen ,  Philip Yu-Shuan Chung ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh ,  Chen-Hua Yu

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L24/13 ,  H01L24/75 ,  H01L2224/81224 ,  H01L2224/81939

Abstract: A method for bonding semiconductor substrates includes placing a die on a substrate and performing a heating process on the die and the substrate to bond the respective first connectors with the respective second connectors. Respective first connectors of a plurality of first connectors on the die contact respective second connectors of a plurality of second connectors on the substrate. The heating process includes placing a mask between a laser generator and the substrate and performing a laser shot. The mask includes a masking layer and a transparent layer. Portions of the masking layer are opaque. The laser passes through a first gap in the masking layer and through the transparent layer to heat a first portion of a top side of the die opposite the substrate.