公开(公告)号：US20250157889A1

公开(公告)日：2025-05-15

申请号：US18582326

申请日：2024-02-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chieh Chang ,  Chih Hsin Yang ,  Mao-Nan Wang ,  Kuan-Hsun Wang ,  Yang-Hsin Shih ,  Yun-Sheng Li ,  Liang-Wei Wang ,  Dian-Hau Chen

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31

Abstract: A method includes forming a first device die comprising forming an integrated circuit on a semiconductor substrate; and forming an interconnect structure on the semiconductor substrate. The interconnect structure has a plurality of metal layers. The method further includes bonding a second device die to the first device die, and forming gap-fill regions surrounding the second device die. In a first formation process, a first TSV is formed to penetrate through the semiconductor substrate, wherein the first TSV has a first width. In a second formation process, a second TSV is formed to penetrate through the semiconductor substrate. The second TSV has a second width different from the first width.

公开(公告)号：US11716910B2

公开(公告)日：2023-08-01

申请号：US17002098

申请日：2020-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hsiang-Ku Shen ,  Liang-Wei Wang ,  Chen-Chiu Huang ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/22 ,  H10N50/01

Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch slop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer.

公开(公告)号：US20220069199A1

公开(公告)日：2022-03-03

申请号：US17002098

申请日：2020-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hsiang-Ku Shen ,  Liang-Wei Wang ,  Chen-Chiu Huang ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/12

Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch stop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer

公开(公告)号：US20250087639A1

公开(公告)日：2025-03-13

申请号：US18401846

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ke-Gang Wen ,  Yu-Bey Wu ,  Tsung-Chieh Hsiao ,  Liang-Wei Wang ,  Dian-Hau Chen

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48

Abstract: A method includes forming first integrated circuits on a front side of a semiconductor substrate of a first device die, forming a trench capacitor extending from a backside of the semiconductor substrate into the semiconductor substrate, and forming a first through-via and a second through-via penetrating through the semiconductor substrate. The trench capacitor is electrically coupled between the first through-via and the second through-via. A second device die is bonded to the first die. The second device die includes second integrated circuits, and power nodes of the second integrated circuits are electrically coupled to the first through-via and the second through-via.

公开(公告)号：US11937515B2

公开(公告)日：2024-03-19

申请号：US17884221

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hsiang-Ku Shen ,  Liang-Wei Wang ,  Chen-Chiu Huang ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/22 ,  H10N50/01

Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch stop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer.

公开(公告)号：US20220059759A1

公开(公告)日：2022-02-24

申请号：US16998911

申请日：2020-08-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Ku Shen ,  Liang-Wei Wang ,  Dian-Hau Chen

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16

Abstract: A method for manufacturing a memory device includes forming a via trench in a substrate and forming a via in the via trench. A lower portion of the via includes a first metal and an upper portion of the via includes a second metal that is different from the first metal. The method further includes forming a magnetic tunneling junction over the via and forming a top electrode over the magnetic tunneling junction.

公开(公告)号：US20250070052A1

公开(公告)日：2025-02-27

申请号：US18493187

申请日：2023-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ke-Gang Wen ,  Chih Hsin Yang ,  Kuan-Hsun Wang ,  Tsung-Chieh Hsiao ,  Liang-Wei Wang ,  Dian-Hau Chen

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/544 ,  H01L23/58 ,  H01L29/66

Abstract: A method includes forming first nanostructures over a first region of a substrate; forming second nanostructures over a second region of the substrate; forming first gate structures around the first nanostructures; replacing the second nanostructures with isolation regions; and forming a seal ring over the substrate, wherein the seal ring is between the first region and the second region.

公开(公告)号：US20220384712A1

公开(公告)日：2022-12-01

申请号：US17884221

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Fan Huang ,  Hsiang-Ku Shen ,  Liang-Wei Wang ,  Chen-Chiu Huang ,  Dian-Hau Chen ,  Yen-Ming Chen

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch stop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer

公开(公告)号：US20250070064A1

公开(公告)日：2025-02-27

申请号：US18403064

申请日：2024-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ke-Gang Wen ,  Yu-Bey Wu ,  Liang-Wei Wang ,  Hsin-Feng Chen ,  Tsung-Chieh Hsiao ,  Chih Chuan Su ,  Dian-Hau Chen

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: An embodiment is a device including a first die and a substrate including a first surface and a second surface opposite the first surface. The device also includes an active device on the first surface of the substrate. The device also includes a first interconnect structure on the first surface of the substrate. The device also includes a through substrate via extending through the first interconnect structure and the substrate to the second surface of the substrate, the through substrate via being electrically coupled to metallization patterns in the first interconnect structure. The device also includes one or more material-filled trench structures extending from the second surface of the substrate into the substrate, the one or more material-filled trench structures being electrically isolated from the through substrate via.

公开(公告)号：US20250046667A1

公开(公告)日：2025-02-06

申请号：US18482217

申请日：2023-10-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Chieh Hsiao ,  Ke-Gang Wen ,  Chih-Pin Chiu ,  Hsin-Feng Chen ,  Yu-Bey Wu ,  Liang-Wei Wang ,  Dian-Hau Chen

IPC: H01L23/367 ,  H01L23/00 ,  H01L25/065

Abstract: A method includes forming a device die including forming integrated circuits on a semiconductor substrate; and forming a thermally conductive pillar extending into the semiconductor substrate. A cooling medium is attached over and contacting the semiconductor substrate to form a package, wherein the cooling medium is thermally coupled to the thermally conductive pillar.