公开(公告)号：US12062686B2

公开(公告)日：2024-08-13

申请号：US16991385

申请日：2020-08-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Guo-Jyun Luo ,  Chen-Chien Chang ,  Chiu-Hua Chung ,  Shiuan-Jeng Lin ,  Han-Zong Pan

IPC: H01L21/285 ,  H01L27/06 ,  H01L27/08 ,  H01L49/02

CPC classification number: H01L28/40 ,  H01L21/2855 ,  H01L27/0629 ,  H01L27/0805

Abstract: The present disclosure relates to a semiconductor device structure. The semiconductor device structure has a first conductive layer disposed over a substrate and a first capacitor dielectric layer comprising a first dielectric material disposed over the first conductive layer. A second conductive layer is over the first capacitor dielectric layer, a second capacitor dielectric layer comprising a second dielectric material is disposed over the second conductive layer, and a third conductive layer is over the second capacitor dielectric layer. A first barrier layer is disposed between an upper surface of the first conductive layer and a lower surface of the first capacitor dielectric layer.

公开(公告)号：US11031320B2

公开(公告)日：2021-06-08

申请号：US16675702

申请日：2019-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Jung Chen ,  Cheng-Hung Wang ,  Tsung-Lin Lee ,  Shiuan-Jeng Lin ,  Chun-Ming Lin ,  Wen-Chih Chiang

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/58 ,  H01L21/02 ,  H01L29/06 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L21/762

Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.

公开(公告)号：US20200176359A1

公开(公告)日：2020-06-04

申请号：US16675702

申请日：2019-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Jung Chen ,  Cheng-Hung Wang ,  Tsung-Lin Lee ,  Shiuan-Jeng Lin ,  Chun-Ming Lin ,  Wen-Chih Chiang

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/58 ,  H01L21/02 ,  H01L21/762 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528 ,  H01L29/06

Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.

公开(公告)号：US10535730B2

公开(公告)日：2020-01-14

申请号：US15964636

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Karthick Murukesan ,  Wen-Chih Chiang ,  Chun Lin Tsai ,  Ker-Hsiao Huo ,  Kuo-Ming Wu ,  Po-Chih Chen ,  Ru-Yi Su ,  Shiuan-Jeng Lin ,  Yi-Min Chen ,  Hung-Chou Lin ,  Yi-Cheng Chiu

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a high voltage metal-oxide-semiconductor (HVMOS) device is integrated with a high voltage junction termination (HVJT) device. In some embodiments, a first drift well and a second drift well are in a substrate. The first and second drift wells border in a ring-shaped pattern and have a first doping type. A peripheral well is in the substrate and has a second doping type opposite the first doping type. The peripheral well surrounds and separates the first and second drift wells. A body well is in the substrate and has the second doping type. Further, the body well overlies the first drift well and is spaced from the peripheral well by the first drift well. A gate electrode overlies a junction between the first drift well and the body well.

公开(公告)号：US20190109189A1

公开(公告)日：2019-04-11

申请号：US16199483

申请日：2018-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Cheng Chiu ,  Wen-Chih Chiang ,  Chun Lin Tsai ,  Kuo-Ming Wu ,  Shiuan-Jeng Lin ,  Yi-Min Chen ,  Hung-Chou Lin ,  Karthick Murukesan

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L23/522 ,  H01L29/10 ,  H01L23/528

Abstract: The present disclosure, in some embodiments, relates to a high voltage resistor device. The device includes a buried well region disposed within a substrate and having a first doping type. A drift region is disposed within the substrate and contacts the buried well region. The drift region has the first doping type. A body region is disposed within the substrate and has a second doping type. The body region laterally contacts the drift region and vertically contacts the buried well region. An isolation structure is over the drift region and a resistor structure is over the isolation structure.

公开(公告)号：US10892360B2

公开(公告)日：2021-01-12

申请号：US16173721

申请日：2018-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chou Lin ,  Yi-Cheng Chiu ,  Karthick Murukesan ,  Yi-Min Chen ,  Shiuan-Jeng Lin ,  Wen-Chih Chiang ,  Chen-Chien Chang ,  Chih-Yuan Chan ,  Kuo-Ming Wu ,  Chun-Lin Tsai

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/40

Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.

公开(公告)号：US20200058647A1

公开(公告)日：2020-02-20

申请号：US16662496

申请日：2019-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Karthick Murukesan ,  Wen-Chih Chiang ,  Chiu-Hua Chung ,  Chun Lin Tsai ,  Kuo-Ming Wu ,  Shiuan-Jeng Lin ,  Tien Sheng Lin ,  Yi-Min Chen ,  Hung-Chou Lin ,  Yi-Cheng Chiu

IPC: H01L27/07 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/78 ,  H01L21/761

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a bootstrap metal-oxide-semiconductor (MOS) device is integrated with a high voltage metal-oxide-semiconductor (HVMOS) device and a high voltage junction termination (HVJT) device. In some embodiments, a drift well is in the semiconductor substrate. The drift well has a first doping type and has a ring-shaped top layout. A first switching device is on the drift well. A second switching device is on the semiconductor substrate, at an indent in a sidewall the drift well. A peripheral well is in the semiconductor substrate and has a second doping type opposite the first doping type. The peripheral well surrounds the drift well, the first switching device, and the second switching device, and further separates the second switching device from the drift well and the first switching device.

公开(公告)号：US20190165180A1

公开(公告)日：2019-05-30

申请号：US15904041

申请日：2018-02-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Lin CHEN ,  Shiuan-Jeng Lin ,  Wen-Chih Chiang ,  Po-Ming Chen ,  Tza-Hao Wang

IPC: H01L29/788 ,  H01L29/49 ,  H01L29/51 ,  H01L29/08 ,  H01L29/423 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/266 ,  H01L29/66

Abstract: A non-volatile memory cell is disclosed. In one example, the non-volatile memory cell includes: a substrate; a first oxide layer over the substrate; a floating gate over the first oxide layer; a second oxide layer over the floating gate; and a control gate at least partially over the second oxide layer. At least one of the first oxide layer and the second oxide layer comprises fluorine.

公开(公告)号：US20190006460A1

公开(公告)日：2019-01-03

申请号：US15694341

申请日：2017-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Cheng Chiu ,  Wen-Chih Chiang ,  Chun Lin Tsai ,  Kuo-Ming Wu ,  Shiuan-Jeng Lin ,  Yi-Min Chen ,  Hung-Chou Lin ,  Karthick Murukesan

IPC: H01L29/06 ,  H01L29/10 ,  H01L23/528 ,  H01L23/522 ,  H01L29/78 ,  H01L29/66

Abstract: The present disclosure relates to a high voltage resistor device that is able to receive high voltages using a small footprint, and an associated method of fabrication. In some embodiments, the high voltage resistor device has a substrate including a first region with a first doping type, and a drift region arranged within the substrate over the first region and having a second doping type. A body region having the first doping type laterally contacts the drift region. A drain region having the second doping type is arranged within the drift region, and an isolation structure is over the substrate between the drain region and the body region. A resistor structure is over the isolation structure and has a high-voltage terminal coupled to the drain region and a low-voltage terminal coupled to a gate structure over the isolation structure.

公开(公告)号：US12068227B2

公开(公告)日：2024-08-20

申请号：US18196988

申请日：2023-05-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Jung Chen ,  Cheng-Hung Wang ,  Tsung-Lin Lee ,  Shiuan-Jeng Lin ,  Chun-Ming Lin ,  Wen-Chih Chiang

IPC: H01L23/48 ,  H01L21/02 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/58 ,  H01L29/06

CPC classification number: H01L23/481 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/31116 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/585 ,  H01L29/0649

Abstract: Structures and methods for reducing process charging damages are disclosed. In one example, a silicon-on-insulator (SOI) structure is disclosed. The SOI structure includes: a substrate, a polysilicon region and an etch stop layer. The substrate includes: a handle layer, an insulation layer arranged over the handle layer, and a buried layer arranged over the insulation layer. The polysilicon region extends downward from an upper surface of the buried layer and terminates in the handle layer. The etch stop layer is located on the substrate. The etch stop layer is in contact with both the substrate and the polysilicon region.