公开(公告)号：US20220365423A1

公开(公告)日：2022-11-17

申请号：US17813165

申请日：2022-07-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Hao LEE ,  Hsi-Cheng HSU ,  Jui-Chun WENG ,  Han-Zong PAN ,  Hsin-Yu CHEN ,  You-Cheng JHANG

IPC: G03F1/64 ,  G03F1/22

Abstract: A portion of a buffer layer on a backside of a substrate of a photomask assembly may be removed prior to formation of one or more capping layers on the backside of the substrate. The one or more capping layers may be formed directly on the backside of the substrate where the buffer layer is removed from the substrate, and a hard mask layer may be formed directly on the one or more capping layers. The one or more capping layers may include a low-stress material to promote adhesion between the one or more capping layers and the substrate, and to reduce and/or minimize peeling and delamination of the capping layer(s) from the substrate. This may reduce the likelihood of damage to the pellicle layer and/or other components of the photomask assembly and/or may increase the yield of an exposure process in which the photomask assembly is used.

公开(公告)号：US20230264945A1

公开(公告)日：2023-08-24

申请号：US18308950

申请日：2023-04-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsi-Cheng HSU ,  Kuo-Hao LEE ,  Jui-Chun WENG ,  Ching-Hsiang HU ,  Ji-Hong CHIANG ,  Lavanya SANAGAVARAPU ,  Chia-Yu LIN ,  Chia-Chun HUNG ,  Jia-Syuan LI ,  Yu-Pei CHIANG

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0005 ,  B81C1/00968 ,  B81C2201/112 ,  B81C2201/115

Abstract: A micro-electromechanical-system (MEMS) device may be formed to include an anti-stiction polysilicon layer on one or more moveable MEMS structures of a device wafer of the MEMS device to reduce, minimize, and/or eliminate stiction between the moveable MEMS structures and other components or structures of the MEMS device. The anti-stiction polysilicon layer may be formed such that a surface roughness of the anti-stiction polysilicon layer is greater than the surface roughness of a bonding polysilicon layer on the surfaces of the device wafer that are to be bonded to a circuitry wafer of the MEMS device. The higher surface roughness of the anti-stiction polysilicon layer may reduce the surface area of the bottom of the moveable MEMS structures, which may reduce the likelihood that the one or more moveable MEMS structures will become stuck to the other components or structures.

公开(公告)号：US20220365424A1

公开(公告)日：2022-11-17

申请号：US17815328

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Hao LEE ,  You-Cheng JHANG ,  Han-Zong PAN ,  Jui-Chun WENG ,  Chiu-Hua CHUNG ,  Sheng-Yuan LIN ,  Hsin-Yu CHEN

IPC: G03F1/64 ,  G03F1/62

Abstract: A photomask assembly may be formed such that stress relief trenches are formed in a pellicle frame of the photomask assembly. The stress relief trenches may reduce or prevent damage to a pellicle that may otherwise result from deformation of the pellicle. The stress relief trenches may be formed in areas of the pellicle frame to allow the pellicle frame to deform with the pellicle, thereby reducing the amount damage to the pellicle caused by the pellicle frame.

公开(公告)号：US20230324787A1

公开(公告)日：2023-10-12

申请号：US18335232

申请日：2023-06-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Hao LEE ,  You-Cheng JHANG ,  Han-Zong PAN ,  Jui-Chun WENG ,  Chiu-Hua CHUNG ,  Sheng-Yuan LIN ,  Hsin-Yu CHEN

IPC: G03F1/64 ,  G03F1/62 ,  G03F7/20

CPC classification number: G03F1/64 ,  G03F1/62 ,  G03F7/70983

Abstract: A photomask assembly may be formed such that stress relief trenches are formed in a pellicle frame of the photomask assembly. The stress relief trenches may reduce or prevent damage to a pellicle that may otherwise result from deformation of the pellicle. The stress relief trenches may be formed in areas of the pellicle frame to allow the pellicle frame to deform with the pellicle, thereby reducing the amount damage to the pellicle caused by the pellicle frame.

公开(公告)号：US20230384664A1

公开(公告)日：2023-11-30

申请号：US18362046

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Hao LEE ,  Hsi-Cheng HSU ,  Jui-Chun WENG ,  Han-Zong PAN ,  Hsin-Yu CHEN ,  You-Cheng JHANG

IPC: G03F1/64 ,  G03F1/22 ,  G03F1/62

CPC classification number: G03F1/64 ,  G03F1/22 ,  G03F1/62

Abstract: A portion of a buffer layer on a backside of a substrate of a photomask assembly may be removed prior to formation of one or more capping layers on the backside of the substrate. The one or more capping layers may be formed directly on the backside of the substrate where the buffer layer is removed from the substrate, and a hard mask layer may be formed directly on the one or more capping layers. The one or more capping layers may include a low-stress material to promote adhesion between the one or more capping layers and the substrate, and to reduce and/or minimize peeling and delamination of the capping layer(s) from the substrate. This may reduce the likelihood of damage to the pellicle layer and/or other components of the photomask assembly and/or may increase the yield of an exposure process in which the photomask assembly is used.

公开(公告)号：US20240402441A1

公开(公告)日：2024-12-05

申请号：US18325219

申请日：2023-05-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Kuo-Hao LEE ,  Xin-Hua HUANG ,  Jung-Kuo TU ,  Kejun XIA ,  Tse-En CHANG

IPC: G02B6/42

Abstract: A photonic package includes an optical die and an electronic die. The optical die has a first side and a second side opposite to the first side. The optical die includes a first grating coupler, a second grating coupler separated from the first grating coupler and an interconnect structure disposed over the first side. The first grating coupler includes a plurality of first segments disposed over the first side, and the second grating coupler includes a plurality of second segments disposed over the first side. The first segments and the second segments include a same material. The interconnect structure is disposed between the electronic die and the optical die. The optical die and the electronic die are electrically connected to each other through the interconnect structure. The first segments are in contact with the interconnect structure, and the second segments are separated from the interconnect structure.

公开(公告)号：US20230352445A1

公开(公告)日：2023-11-02

申请号：US18347067

申请日：2023-07-05

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsi-Cheng HSU ,  Jui-Chun WENG ,  Ching-Hsiang HU ,  Ji-Hong CHIANG ,  Kuo-Hao LEE ,  Chia-Yu LIN ,  Chia-Chun HUNG ,  Yen-Chieh TU ,  Chien-Tai SU ,  Hsin-Yu CHEN

IPC: H01L23/00 ,  H01L23/544 ,  H01L25/065

CPC classification number: H01L24/94 ,  H01L23/562 ,  H01L23/544 ,  H01L24/32 ,  H01L25/0657

Abstract: Alignment of devices formed on substrates that are to be bonded may be achieved through the use of scribe lines between the devices, where the scribe lines progressively increase or decrease in size from a center to an edge of one or more of the substrates to compensate for differences in the thermal expansion rates of the substrates. The devices on the substrates are brought into alignment as the substrates are heated during a bonding operation due to the progressively increased or decreased sizes of the scribe lines. The scribe lines may be arranged in a single direction in a substrate to compensate for thermal expansion along a single axis of the substrate or may be arranged in a plurality of directions to compensate for actinomorphic thermal expansion.