公开(公告)号：US20230152828A1

公开(公告)日：2023-05-18

申请号：US18089433

申请日：2022-12-27

Applicant: Texas Instruments Incorporated

Inventor： Rinu Mathew ,  Harikrishna P ,  Venkatesh Kadlimatti

IPC: G05F1/56 ,  H03F3/45

CPC classification number: G05F1/56 ,  H03F3/45475

Abstract: In described examples, a low dropout voltage regulator includes an input voltage terminal, a resistive element, first and second transistors, an output terminal, a differential amplifier, and first and second saturation prevention circuits. The resistive element is coupled between the input voltage terminal and a gate of the first transistor. The output terminal is coupled to the drain of the first transistor and the source of the second transistor. A first input of the differential amplifier receives a reference voltage, and a second input is coupled to the output terminal. The first saturation prevention circuit provides a first clamp current to the differential amplifier output if the gate-source voltage of the first transistor is less than a first threshold voltage. The second saturation prevention circuit provides a second clamp current to the differential amplifier output if the gate-source voltage of the second transistor is greater than a second threshold voltage.

公开(公告)号：US20240361794A1

公开(公告)日：2024-10-31

申请号：US18309340

申请日：2023-04-28

Applicant: Texas Instruments Incorporated

Inventor： Venkatesh Kadlimatti ,  Aritra Chowdhury ,  Harikrishna P

IPC: G05F3/24 ,  G05F1/565 ,  G05F3/26

CPC classification number: G05F3/247 ,  G05F1/565 ,  G05F3/262

Abstract: In described examples, a voltage glitch detector includes a current source, a latch, and first, second, third, fourth, and fifth transistors. A source of the third transistor is coupled to a source of the second transistor, and a gate and drain of the third transistor is coupled to gates of the first and second transistors and a first terminal of the current source. A drain of the fourth transistor is coupled to a drain of the first transistor and an input of the latch. A source of the fifth transistor is coupled to a source of the fourth transistor and the second terminal of the current source. A gate and drain of the fifth transistor is coupled to a gate of the fourth transistor and a drain of the second transistor.