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公开(公告)号：US20160041831A1
公开(公告)日：2016-02-11
申请号：US14452700
申请日：2014-08-06
Applicant: Texas Instruments Incorporated
Inventor： Asaf Carmeli , Ben Gilboa , Avi Baum , Barak Cherches , Mukesh Kumar
CPC classification number: G06F9/4418 , G06F1/3287 , G06F13/1673 , G06F13/28 , G06F13/4291 , Y02D10/14 , Y02D10/151
Abstract: A system and method is disclosed that enables a peripheral or slave device to seamlessly transition in and out of sleep state while remaining completely transparent to host software. When the device is in a sleep mode and incoming data is detected, the device begins a wake-up procedure and data is routed to a first, transitional memory. The size of the transitional memory is selected such that it is capable of buffering data received during time required for the system memory to stabilize from wake-up. Once a second, extended memory is stabilized, the data is buffered from the transitional memory to the extended memory. The device resumes normal operation when its processor has initialized and can read data from the extended memory.
Abstract translation: 公开了一种系统和方法，其使得外围设备或从设备无缝地转换进入和离开休眠状态，同时对主机软件保持完全透明。 当设备处于睡眠模式并且检测到传入数据时，设备开始唤醒过程，数据被路由到第一个过渡存储器。 选择过渡存储器的大小，使得其能够缓冲系统存储器在唤醒期间稳定所需的时间期间接收到的数据。 一旦一秒钟，扩展存储器就被稳定，数据就从缓冲存储器过渡到扩展存储器。 当处理器初始化并且可以从扩展内存读取数据时，该设备恢复正常操作。
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公开(公告)号：US09459886B2
公开(公告)日：2016-10-04
申请号：US14452700
申请日：2014-08-06
Applicant: Texas Instruments Incorporated
Inventor： Asaf Carmeli , Ben Gilboa , Avi Baum , Barak Cherches , Mukesh Kumar
CPC classification number: G06F9/4418 , G06F1/3287 , G06F13/1673 , G06F13/28 , G06F13/4291 , Y02D10/14 , Y02D10/151
Abstract: A system and method is disclosed that enables a peripheral or slave device to seamlessly transition in and out of sleep state while remaining completely transparent to host software. When the device is in a sleep mode and incoming data is detected, the device begins a wake-up procedure and data is routed to a first, transitional memory. The size of the transitional memory is selected such that it is capable of buffering data received during time required for the system memory to stabilize from wake-up. Once a second, extended memory is stabilized, the data is buffered from the transitional memory to the extended memory. The device resumes normal operation when its processor has initialized and can read data from the extended memory.
Abstract translation: 公开了一种系统和方法，其使得外围设备或从设备无缝地转换进入和离开休眠状态，同时对主机软件保持完全透明。 当设备处于睡眠模式并且检测到传入数据时，设备开始唤醒过程，数据被路由到第一个过渡存储器。 选择过渡存储器的大小，使得其能够缓冲系统存储器在唤醒期间稳定所需的时间期间接收到的数据。 一旦一秒钟，扩展存储器就被稳定，数据就从缓冲存储器过渡到扩展存储器。 当处理器初始化并且可以从扩展内存读取数据时，该设备恢复正常操作。
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公开(公告)号：US08698539B1
公开(公告)日：2014-04-15
申请号：US13739228
申请日：2013-01-11
Applicant: Texas Instruments Incorporated
Inventor： Jasbir Singh Nayyar , Sreenath Narayanan Potty , Mukesh Kumar , Vivek Singhal
IPC: G06F1/04
CPC classification number: G06F1/04
Abstract: A clock generation circuit in an IC is provided for mitigating signal interferences caused by an aggressor block operable on a first clock signal with a frequency range of a victim block. The clock generation circuit includes a gating circuit configured to perform gating of a second clock signal to generate a third clock signal based on control signal. An average frequency of the third clock signal is substantially matched to a frequency of the first clock signal, and harmonics of the third clock signal do not interfere with the frequency range of the victim block. The clock generation circuit further includes a FIFO buffer circuit configured to receive the first clock signal as a write clock and the third clock signal as read clock, and a control circuit for generating the control signal based on an occupancy level of FIFO buffer circuit and a plurality of random numbers.
Abstract translation: 提供了IC中的时钟发生电路，用于减轻由在受害者块的频率范围内的第一时钟信号上可操作的攻击者块引起的信号干扰。 时钟发生电路包括门控电路，其被配置为基于控制信号执行第二时钟信号的门控以产生第三时钟信号。 第三时钟信号的平均频率基本上与第一时钟信号的频率相匹配，并且第三时钟信号的谐波不会干扰受害者块的频率范围。 时钟生成电路还包括：FIFO缓冲电路，被配置为将第一时钟信号作为写时钟接收，第三时钟信号作为读时钟;以及控制电路，用于基于FIFO缓冲电路的占用电平和 多个随机数。
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