公开(公告)号：US11915931B2

公开(公告)日：2024-02-27

申请号：US17406612

申请日：2021-08-19

Applicant: Tokyo Electron Limited

Inventor： Choong-man Lee ,  Soo Doo Chae ,  Angelique Raley ,  Qiaowei Lou ,  Toshio Hasegawa ,  Yoshihiro Kato

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L21/0274 ,  H01L21/0332 ,  H01L21/31144

Abstract: A method for fabricating a semiconductor device is described that includes forming a base layer over a top layer of a substrate, the base layer includes a silicon based dielectric having a thickness less than or equal to 5 nm and greater than or equal to 0.5 nm; forming a photoresist layer over the base layer, the photoresist including a first side and an opposite second side; exposing a first portion of the photoresist layer to a pattern of extreme ultraviolet (EUV) radiation from the first side; exposing a second portion of the photoresist layer with a pattern of electron flux from the second side, the electron flux being directed into the photoresist layer from the base layer in response to the EUV radiation; developing the exposed photoresist layer to form a patterned photoresist layer; and transferring the pattern of the patterned photoresist layer to the base layer and the top layer.

公开(公告)号：US20250164891A1

公开(公告)日：2025-05-22

申请号：US18511327

申请日：2023-11-16

Applicant: Tokyo Electron Limited

Inventor： Soo Doo Chae ,  Jiwoo Kim ,  Hojin Kim ,  Choong-man Lee ,  Tek Po Rinus Lee ,  Ornella Sathoud

IPC: G03F7/00 ,  G03F1/46 ,  G03F1/50 ,  G03F1/80 ,  G03F7/004 ,  G03F7/075

Abstract: An example lithography stack includes a first layer including an organic material, a second layer disposed over the first layer, where the second layer includes a dielectric material. The lithography stack includes a third layer disposed over the second layer, where the third layer includes a metallic material. The lithography stack includes a fourth layer disposed over the third layer, where the fourth layer includes an extreme ultraviolet (EUV) photoresist.

公开(公告)号：US20230054125A1

公开(公告)日：2023-02-23

申请号：US17406612

申请日：2021-08-19

Applicant: Tokyo Electron Limited

Inventor： Choong-man Lee ,  Soo Doo Chae ,  Angelique Raley ,  Qiaowei Lou ,  Toshio Hasegawa ,  Yoshihiro Kato

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/311

Abstract: A method for fabricating a semiconductor device is described that includes forming a base layer over a top layer of a substrate, the base layer includes a silicon based dielectric having a thickness less than or equal to 5 nm and greater than or equal to 0.5 nm; forming a photoresist layer over the base layer, the photoresist including a first side and an opposite second side; exposing a first portion of the photoresist layer to a pattern of extreme ultraviolet (EUV) radiation from the first side; exposing a second portion of the photoresist layer with a pattern of electron flux from the second side, the electron flux being directed into the photoresist layer from the base layer in response to the EUV radiation; developing the exposed photoresist layer to form a patterned photoresist layer; and transferring the pattern of the patterned photoresist layer to the base layer and the top layer.