公开(公告)号：US20230012093A1

公开(公告)日：2023-01-12

申请号：US17781803

申请日：2020-12-04

Applicant: Tokyo Institute of Technology

Inventor： Kuniyuki KAKUSHIMA ,  Hiroshi FUNAKUBO ,  Shun-ichiro OHMI ,  Joel MOLINA REYES ,  Ichiro FUJIWARA ,  Atsushi HORI ,  Takao SHIMIZU ,  Yoshiko NAKAMURA ,  Takanori MIMURA

IPC: H01L27/11502 ,  H01L27/11585 ,  H01L27/11 ,  G11C11/22 ,  H01L27/11524

Abstract: The invention provides a non-volatile storage element and non-volatile storage device employing a ferroelectric material with low power consumption, excellent high reliability, and especially write/erase endurance, which can be mixed with advanced CMOS logic. The non-volatile storage element has at least a first conductive layer, a second conductive layer, and a ferroelectric layer composed of a metal oxide between both conductive layers, with a buffer layer having oxygen ion conductivity situated between the ferroelectric layer and the first conductive layer and/or second conductive layer. An interface layer composed of a single-layer film or a multilayer film may be also provided between the first conductive layer and the ferroelectric layer, the interface layer as a whole having higher dielectric constant than silicon oxide, and when the buffer layer is present between the first conductive layer and the ferroelectric layer, the interface layer is situated between the first conductive layer and the buffer layer. The non-volatile storage device comprises at least a memory cell array comprising low-power-consumption ferroelectric memory elements formed in a two-dimensional or three-dimensional configuration, and a control circuit. The ferroelectric layer is scalable to 10 nm or smaller and is fabricated at a low temperature of ≤400° C., and is subjected to low temperature thermal annealing treatment at ≤400° C. after the buffer layer has been formed, to provide high reliability.