公开(公告)号：US08304905B2

公开(公告)日：2012-11-06

申请号：US13192049

申请日：2011-07-27

Applicant: Satoshi Matsui ,  Tsuyoshi Eda ,  Akira Matsumoto ,  Yoshitaka Kyougoku ,  Shinji Watanabe ,  Hirokazu Honda

Inventor： Satoshi Matsui ,  Tsuyoshi Eda ,  Akira Matsumoto ,  Yoshitaka Kyougoku ,  Shinji Watanabe ,  Hirokazu Honda

IPC: H01L23/48 ,  H01L29/40

CPC classification number: H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/11622 ,  H01L2224/11849 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/1354 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A semiconductor device includes a semiconductor chip, wiring formed thereon, a first insulating film formed on the wiring, provided with a first opening, a pad electrode formed so as to be in contact with the wiring, a second insulating film formed on the pad electrode film, provided with a second opening, and a flip chip bump formed so as to be in contact with the pad electrode film. In this case, the second insulating film exists between the flip chip bump and the pad electrode film, in a region directly underneath the outer edge of the flip chip bump, as seen in a plan view, and the outer edge of the flip chip bump is formed in a region inside the outer edge of the pad electrode film.

Abstract translation: 半导体器件包括半导体芯片，形成在其上的布线，形成在布线上的第一绝缘膜，设置有第一开口，形成为与布线接触的焊盘电极，形成在焊盘电极上的第二绝缘膜 具有第二开口的膜，以及形成为与焊盘电极膜接触的倒装芯片凸块。 在这种情况下，如俯视图所示，第二绝缘膜存在于倒装芯片凸块和焊盘电极膜之间的直接在倒装芯片凸块的外边缘下方的区域中，并且倒装芯片凸块的外边缘 形成在焊盘电极膜的外边缘内的区域中。

公开(公告)号：US20100013092A1

公开(公告)日：2010-01-21

申请号：US12458328

申请日：2009-07-08

Applicant: Tsuyoshi Eda

Inventor： Tsuyoshi Eda

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H05K3/3436 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/1147 ,  H01L2224/13012 ,  H01L2224/13022 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01059 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H05K3/3463 ,  H05K2201/10992 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/13099

Abstract: Provided is a semiconductor device having a bump structure which is capable of resolving inconvenience in mounting. The semiconductor device comprises: an electrode pad; and a columnar bump formed on the electrode pad, the columnar bump comprising: a first high melting point metal layer (14) formed on the electrode pad; a first solder (15) formed on the first high melting point metal layer (14); a second high melting point metal layer (16) formed on the first solder (15); and a second solder (17) which is formed on the second high melting point metal layer (16) and is connected to an external.

Abstract translation: 提供了具有能够解决安装不便的凸块结构的半导体器件。 该半导体器件包括：电极焊盘; 和形成在所述电极焊盘上的柱状凸起，所述柱状凸起包括：形成在所述电极焊盘上的第一高熔点金属层（14） 形成在第一高熔点金属层（14）上的第一焊料（15）; 形成在第一焊料（15）上的第二高熔点金属层（16）; 和形成在第二高熔点金属层（16）上并与外部连接的第二焊料（17）。

公开(公告)号：US20090224375A1

公开(公告)日：2009-09-10

申请号：US12379364

申请日：2009-02-19

Applicant: Tsuyoshi Eda

Inventor： Tsuyoshi Eda

IPC: H01L23/58 ,  H01L21/469

CPC classification number: H01L24/05 ,  H01L23/293 ,  H01L23/3192 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05558 ,  H01L2224/05564 ,  H01L2224/05572 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

Abstract: The present invention provides a semiconductor device for which thermal stress at mounting is reduced and a reduction in reliability with regard to moisture absorption is prevented. The semiconductor device includes a uppermost metal layer 12, a solder bump 17, metals 15 and 16 which connect an uppermost metal layer 12 and the solder bump 17, and, a polyimide multilayer 14 having formed therein an opening 14x in which the metals 15 and 16 are provided. The polyimide multilayer 14 includes a first polyimide layer 14A and a second polyimide layer 14B formed on the first polyimide layer 14A. The second polyimide layer 14B is softer than the first polyimide layer 14A. A thermal stress at mounting is reduced by the second polyimide layer 14B. Since the first polyimide layer 14A has a higher strength than the second polyimide layer 14B, even if cracking occurs in the second polyimide layer 14B, the cracks are prevented from developing in the first polyimide layer 14A.

Abstract translation: 本发明提供了一种半导体器件，其在安装时的热应力降低，并且防止了关于吸湿性的可靠性的降低。 半导体器件包括最上层金属层12，焊料凸点17，连接最上层金属层12和焊料凸块17的金属15和16以及形成有开口14x的聚酰亚胺多层14，金属15和 16。 聚酰亚胺层14包括形成在第一聚酰亚胺层14A上的第一聚酰亚胺层14A和第二聚酰亚胺层14B。 第二聚酰亚胺层14B比第一聚酰亚胺层14A软。 通过第二聚酰亚胺层14B减少安装时的热应力。 由于第一聚酰亚胺层14A具有比第二聚酰亚胺层14B更高的强度，所以即使在第二聚酰亚胺层14B中发生裂纹，也可以防止在第一聚酰亚胺层14A中产生裂纹。

公开(公告)号：US08310267B2

公开(公告)日：2012-11-13

申请号：US12823674

申请日：2010-06-25

Applicant: Toru Sekiguchi ,  Tsuyoshi Eda

Inventor： Toru Sekiguchi ,  Tsuyoshi Eda

IPC: G01R31/02 ,  G01R31/3187

CPC classification number: G01R31/2853 ,  G01R27/14

Abstract: In order to reduce the number of electrodes included in test patterns, the semiconductor integrated circuit includes, a plurality of first and second chains, a first common electrode connected to one end of each first chain, a second common electrode connected to one end of each second chain, and a plurality of selection electrodes. Each selection electrode is connected to the other end of any one of the plurality of first chains and to the other end of any one of the plurality of second chains. When a test target chain is selected from the plurality of first chains, a first reference voltage is applied to the first common electrode, a second reference voltage is applied to a target selection electrode that is connected to the test target chain, and a current flowing in the target selection electrode is measured to obtain a resistance value of the test target chain.

Abstract translation: 为了减少包括在测试图案中的电极的数量，半导体集成电路包括多个第一和第二链，连接到每个第一链的一端的第一公共电极，连接到每个第一链的一端的第二公共电极 第二链和多个选择电极。 每个选择电极连接到多个第一链中的任一个的另一端和多个第二链中的任一个的另一端。 当从多个第一链中选择测试目标链时，将第一参考电压施加到第一公共电极，将第二参考电压施加到连接到测试目标链的目标选择电极，并且流过电流 测量目标选择电极以获得测试目标链的电阻值。

公开(公告)号：US07936075B2

公开(公告)日：2011-05-03

申请号：US12379364

申请日：2009-02-19

Applicant: Tsuyoshi Eda

Inventor： Tsuyoshi Eda

IPC: H01L23/48

CPC classification number: H01L24/05 ,  H01L23/293 ,  H01L23/3192 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05558 ,  H01L2224/05564 ,  H01L2224/05572 ,  H01L2224/13006 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

Abstract: The present invention provides a semiconductor device for which thermal stress at mounting is reduced and a reduction in reliability with regard to moisture absorption is prevented. The semiconductor device includes a uppermost metal layer 12, a solder bump 17, metals 15 and 16 which connect an uppermost metal layer 12 and the solder bump 17, and, a polyimide multilayer 14 having formed therein an opening 14x in which the metals 15 and 16 are provided. The polyimide multilayer 14 includes a first polyimide layer 14A and a second polyimide layer 14B formed on the first polyimide layer 14A. The second polyimide layer 14B is softer than the first polyimide layer 14A. A thermal stress at mounting is reduced by the second polyimide layer 14B. Since the first polyimide layer 14A has a higher strength than the second polyimide layer 14B, even if cracking occurs in the second polyimide layer 14B, the cracks are prevented from developing in the first polyimide layer 14A.

Abstract translation: 本发明提供了一种半导体器件，其在安装时的热应力降低，并且防止了关于吸湿性的可靠性的降低。 半导体器件包括最上层金属层12，焊料凸点17，连接最上层金属层12和焊料凸块17的金属15和16以及形成有开口14x的聚酰亚胺多层14，金属15和 16。 聚酰亚胺层14包括形成在第一聚酰亚胺层14A上的第一聚酰亚胺层14A和第二聚酰亚胺层14B。 第二聚酰亚胺层14B比第一聚酰亚胺层14A软。 通过第二聚酰亚胺层14B减少安装时的热应力。 由于第一聚酰亚胺层14A具有比第二聚酰亚胺层14B更高的强度，所以即使在第二聚酰亚胺层14B中发生裂纹，也可以防止在第一聚酰亚胺层14A中产生裂纹。