公开(公告)号：US20220077179A1

公开(公告)日：2022-03-10

申请号：US17065508

申请日：2020-10-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hock Chun Chin

IPC: H01L27/11582 ,  H01L27/11568

Abstract: A three-dimensional (3D) memory device includes a channel structure extending along a first direction and a control gate structure extending along a second direction around the channel structure. Preferably, channel structure includes a negative capacitance (NC) insulating layer, a charge trap structure, and a channel layer, in which the NC insulating layer includes HfZrOx and the charge trap structure includes a blocking layer, a charge trap layer, and a tunneling layer.

公开(公告)号：US11832446B2

公开(公告)日：2023-11-28

申请号：US17065508

申请日：2020-10-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hock Chun Chin

IPC: H01L29/10 ,  H01L27/11 ,  H10B43/27 ,  H10B43/30 ,  H10B51/20 ,  H01L21/28 ,  H01L29/78 ,  H01L29/792 ,  H10B43/50 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L29/40111 ,  H10B43/30 ,  H10B51/20 ,  H01L29/40117 ,  H01L29/78391 ,  H01L29/7926 ,  H10B43/35 ,  H10B43/50

Abstract: A three-dimensional (3D) memory device includes a channel structure extending along a first direction and a control gate structure extending along a second direction around the channel structure. Preferably, channel structure includes a negative capacitance (NC) insulating layer, a charge trap structure, and a channel layer, in which the NC insulating layer includes HfZrOx and the charge trap structure includes a blocking layer, a charge trap layer, and a tunneling layer.

公开(公告)号：US09911847B1

公开(公告)日：2018-03-06

申请号：US15647286

申请日：2017-07-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hock Chun Chin ,  Lanxiang Wang ,  Hong Liao ,  Chao Jiang ,  Chow Yee Lim

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/78391 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/28291 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/7881 ,  H01L29/792

Abstract: A non-volatile memory device includes a substrate, a gate stack structure, an erase gate structure, and a ferroelectric layer. The gate stack structure is disposed on the substrate. The erase gate structure is disposed on the substrate and disposed at a first side of the gate stack structure. The ferroelectric layer is disposed on a sidewall of the gate stack structure, and the ferroelectric layer is disposed between the gate stack structure and the erase gate structure. The ferroelectric layer disposed between the gate stack structure and the erase gate structure may be used to forma negative capacitance effect for amplifying the voltage applied to the erase gate structure. The purpose of reducing power consumption may be achieved accordingly.