公开(公告)号：US20180374856A1

公开(公告)日：2018-12-27

申请号：US15632378

申请日：2017-06-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Wen Chen ,  Chi-Chang Shuai ,  Hsien-Hung Tsai

IPC: H01L27/108 ,  H01L27/11 ,  H01L29/24

Abstract: The present invention provides a semiconductor memory circuit, the semiconductor memory circuit includes a static random access memory (SRAM), having a first storage node and a second storage node, a dynamic oxide semiconductor random access memory (DOSRAM), electrically connected to the SRAM, wherein the DOSRAM includes a first oxide semiconductor field effect transistor (OSFET) and a capacitor, wherein a source of the first OSFET is electrically connected to the first storage node, and a drain of the first OSFET is electrically connected to the capacitor, and a second transistor and a third oxide semiconductor field effect transistor (OSFET), wherein a drain of the second transistor is electrically connected to the second storage node, a source of the third OSFET is electrically connected to the capacitor, and a drain of the third OSFET is electrically connected to a gate of the third transistor.

公开(公告)号：US10032777B1

公开(公告)日：2018-07-24

申请号：US15613288

申请日：2017-06-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Wen Chen ,  Chi-Chang Shuai ,  Hung-Chan Lin ,  Ting-Hao Chang ,  Hsien-Hung Tsai

IPC: H01L27/108 ,  G06F12/0846

Abstract: An array of dynamic random access memory cells includes a first set of memory cell pairs in a first row, a second set of memory cells in a second row, and a first set of bit line contacts in the first row. The second set of memory cell pairs are disposed adjacent to the first set of memory cell pairs, and each two of the memory cell pairs in the second row include a common S/D region. Each of the first set of bit line contacts is electrically coupled to each of the common S/D regions of the memory cell pairs in the second row respectively.

公开(公告)号：US10276578B2

公开(公告)日：2019-04-30

申请号：US15632378

申请日：2017-06-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Wen Chen ,  Chi-Chang Shuai ,  Hsien-Hung Tsai

IPC: H01L27/108 ,  H01L27/11 ,  H01L29/24

Abstract: The present invention provides a semiconductor memory circuit, the semiconductor memory circuit includes a static random access memory (SRAM), having a first storage node and a second storage node, a dynamic oxide semiconductor random access memory (DOSRAM), electrically connected to the SRAM, wherein the DOSRAM includes a first oxide semiconductor field effect transistor (OSFET) and a capacitor, wherein a source of the first OSFET is electrically connected to the first storage node, and a drain of the first OSFET is electrically connected to the capacitor, and a second transistor and a third oxide semiconductor field effect transistor (OSFET), wherein a drain of the second transistor is electrically connected to the second storage node, a source of the third OSFET is electrically connected to the capacitor, and a drain of the third OSFET is electrically connected to a gate of the third transistor.