公开(公告)号：US10062705B1

公开(公告)日：2018-08-28

申请号：US15487404

申请日：2017-04-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei Xu ,  JiZhou Han ,  Wang Xiang

IPC: H01L27/11568 ,  H01L27/11573 ,  H01L21/02 ,  H01L29/51 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L21/02164 ,  H01L27/11573 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: A method of manufacturing a flash memory includes providing a substrate, a memory gate on the substrate, a hard mask on the memory gate, a spacer on a sidewall of the memory gate, and a select gate disposed on a sidewall of the spacer. A first silicon oxide layer is formed to conformally cover the memory gate, the hard mask, the spacer, and the select gate. A thickness of the first silicon oxide layer is smaller than 0.54 of a thickness of the hard mask. Later, the first silicon oxide layer is thinned by a dry etching process. After that, the first silicon oxide layer and the hard mask are entirely removed by a wet etching process.

公开(公告)号：US10916634B2

公开(公告)日：2021-02-09

申请号：US16417542

申请日：2019-05-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei Xu ,  Wenbo Ding ,  Yu-Yang Chen ,  Wang Xiang

IPC: H01L21/28 ,  H01L27/11563 ,  H01L21/033

Abstract: A method of fabricating a semiconductor device includes forming a memory gate and a hard mask layer on the memory gate, forming a select gate on a sidewall of the memory gate and the hard mask layer, performing a selective oxidation process to form an oxide layer on the hard mask layer and the select gate, wherein a portion of the oxide layer on the select gate is thicker than a portion of the oxide layer on the hard mask layer, and removing the oxide layer on the hard mask layer and the hard mask layer to expose a top surface of the memory gate.