公开(公告)号：US09484223B2

公开(公告)日：2016-11-01

申请号：US14985448

申请日：2015-12-31

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Chung-W. Ho

IPC: H01L21/00 ,  H01L21/48 ,  H01L21/683 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L21/4857 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2221/6835 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A coreless packaging substrate includes: a circuit buildup structure having at least a dielectric layer, a wiring layer and a plurality of conductive elements, a plurality of electrical pads embedded in the dielectric layer of the circuit buildup structure, a plurality of metal bumps formed on the wiring layer of the circuit buildup structure, and a dielectric passivation layer formed on the surface of the circuit buildup structure and the metal bumps with the metal bumps exposed from the dielectric passivation layer. The metal bumps each have a metal column portion and a wing portion integrally connected to the metal column portion, such that the bonding force between the metal bumps and a semiconductor chip can be enhanced by the entire top surface of the wing portions of the metal bumps being completely exposed.

Abstract translation: 无芯封装基板包括：具有至少介电层，布线层和多​​个导电元件的电路积层结构，嵌入电路堆积结构的电介质层中的多个电焊盘，形成在 电路积层结构的布线层，以及形成在电路堆积结构的表面上的电介质钝化层和金属凸块，金属凸块从电介质钝化层露出。 金属凸块各自具有金属柱部分和与金属柱部分一体地连接的翼部，使得金属凸块和半导体芯片之间的结合力可以通过金属凸块的翼部的整个顶表面增强 被完全暴露。

公开(公告)号：US20160111301A1

公开(公告)日：2016-04-21

申请号：US14985448

申请日：2015-12-31

Applicant: Unimicron Technology Corp.

Inventor： Tzyy-Jang Tseng ,  Chung-W. Ho

IPC: H01L21/48 ,  H01L21/683

CPC classification number: H01L21/4857 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L2221/6835 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A coreless packaging substrate includes: a circuit buildup structure having at least a dielectric layer, a wiring layer and a plurality of conductive elements, a plurality of electrical pads embedded in the dielectric layer of the circuit buildup structure, a plurality of metal bumps formed on the wiring layer of the circuit buildup structure, and a dielectric passivation layer formed on the surface of the circuit buildup structure and the metal bumps with the metal bumps exposed from the dielectric passivation layer. The metal bumps each have a metal column portion and a wing portion integrally connected to the metal column portion, such that the bonding force between the metal bumps and a semiconductor chip can be enhanced by the entire top surface of the wing portions of the metal bumps being completely exposed.

Abstract translation: 无芯封装基板包括：具有至少介电层，布线层和多​​个导电元件的电路积层结构，嵌入电路堆积结构的电介质层中的多个电焊盘，形成在 电路积层结构的布线层，以及形成在电路堆积结构的表面上的电介质钝化层和金属凸块，金属凸块从电介质钝化层露出。 金属凸块各自具有金属柱部分和与金属柱部分一体地连接的翼部，使得金属凸块和半导体芯片之间的结合力可以通过金属凸块的翼部的整个顶表面增强 被完全暴露。