公开(公告)号：US20230185530A1

公开(公告)日：2023-06-15

申请号：US17925048

申请日：2021-05-10

Applicant: Universität Stuttgart

Inventor： Markus GRÖZING

IPC: G06F7/523 ,  G06F7/544 ,  H03M1/82

CPC classification number: G06F7/523 ,  G06F7/5443 ,  H03M1/82

Abstract: The present invention relates to a method for the analogue multiplication and/or calculation of a scalar product, with a circuit assembly, which has a series circuit comprising a first FET and a second FET, or FET array, serving as a current source, a charging device, and a capacitance, which can be precharged by way of the charging device, and can be discharged by way of the series circuit of the first FET and the second FET, or FET array. The capacitance is initially precharged for the multiplication of a first value by a second value. The first value, encoded as the pulse width of a voltage pulse, is applied to the gate of the first FET, and the second value, encoded as the voltage amplitude, is applied to the gate of the second FET. By this means the capacitance is discharged, for the period of time of the voltage pulse, with a discharge current, which is specified by the voltage amplitude applied to the second FET. The result of the multiplication can then be determined from the residual charge or residual voltage of the capacitance. The method operates very energy-efficiently and can advantageously be used for the execution of calculations in neurons of an artificial neural network.