公开(公告)号：US20240256453A1

公开(公告)日：2024-08-01

申请号：US18160194

申请日：2023-01-26

Applicant: VMware LLC

Inventor： Andreas Georg Nowatzyk ,  Pratap Subrahmanyam ,  Isam Wadih Akkawi ,  Adarsh Seethanadi Nayak ,  Nishchay Dua

IPC: G06F12/0846 ,  G06F12/0891

CPC classification number: G06F12/0846 ,  G06F12/0891

Abstract: Techniques for implementing a hardware-based cache controller in, e.g., a tiered memory computer system are provided. In one set of embodiments, the cache controller can flexibly operate in a number of different modes that aid the OS/hypervisor of the computer system in managing and optimizing its use of the system's memory tiers. In another set of embodiments, the cache controller can implement a hardware architecture that enables it to significantly reduce the probability of tag collisions, decouple cache capacity management from cache lookup and allocation, and handle multiple concurrent cache transactions.

公开(公告)号：US20240256439A1

公开(公告)日：2024-08-01

申请号：US18160184

申请日：2023-01-26

Applicant: VMware LLC

Inventor： Andreas Georg Nowatzyk ,  Pratap Subrahmanyam ,  Isam Wadih Akkawi ,  Adarsh Seethanadi Nayak ,  Nishchay Dua

IPC: G06F12/02 ,  G06F12/0864 ,  G06F12/0895

CPC classification number: G06F12/0246 ,  G06F12/0864 ,  G06F12/0895

Abstract: Techniques for implementing a hardware-based cache controller in, e.g., a tiered memory computer system are provided. In one set of embodiments, the cache controller can flexibly operate in a number of different modes that aid the OS/hypervisor of the computer system in managing and optimizing its use of the system's memory tiers. In another set of embodiments, the cache controller can implement a hardware architecture that enables it to significantly reduce the probability of tag collisions, decouple cache capacity management from cache lookup and allocation, and handle multiple concurrent cache transactions.

公开(公告)号：US20240256446A1

公开(公告)日：2024-08-01

申请号：US18160172

申请日：2023-01-26

Applicant: VMware LLC

Inventor： Andreas Georg Nowatzyk ,  Pratap Subrahmanyam ,  Isam Wadih Akkawi ,  Adarsh Seethanadi Nayak ,  Nishchay Dua

IPC: G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/30

Abstract: Techniques for implementing a hardware-based cache controller in, e.g., a tiered memory computer system are provided. In one set of embodiments, the cache controller can flexibly operate in a number of different modes that aid the OS/hypervisor of the computer system in managing and optimizing its use of the system's memory tiers. In another set of embodiments, the cache controller can implement a hardware architecture that enables it to significantly reduce the probability of tag collisions, decouple cache capacity management from cache lookup and allocation, and handle multiple concurrent cache transactions.