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    EEPROM MEMORY CELL WITH FIRST-DOPANT-TYPE CONTROL GATE TRANSISTOR, AND SECOND-DOPANT TYPE PROGRAM/ERASE AND ACCESS TRANSISTORS FORMED IN COMMON WELL
    3.
    发明申请
    EEPROM MEMORY CELL WITH FIRST-DOPANT-TYPE CONTROL GATE TRANSISTOR, AND SECOND-DOPANT TYPE PROGRAM/ERASE AND ACCESS TRANSISTORS FORMED IN COMMON WELL 有权
    具有第一种类型控制栅极晶体管的EEPROM存储器单元和通常形成的第二种类型的程序/擦除和访问晶体管

    公开(公告)号：US20090014772A1

    公开(公告)日：2009-01-15

    申请号：US12233294

    申请日：2008-09-18

    Applicant: Nirmal Ratnakumar ,  Venkatraman Prabhakar ,  David Kuan-Yu Liu

    Inventor： Nirmal Ratnakumar ,  Venkatraman Prabhakar ,  David Kuan-Yu Liu

    IPC: H01L29/788

    CPC classification number: G11C16/0441 ,  G11C16/3427 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

    Abstract: A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell.

    Abstract translation: 一种包括多个存储单元的存储器件，每个存储器单元具有与编程/擦除PMOS晶体管共享浮置栅极的控制栅极NMOS晶体管，该晶体管又与访问PMOS晶体管串联连接。 存储单元形成在形成在P基板中的公共N阱中，NMOS晶体管形成在p掺杂的凹穴或基底中。 编程/擦除PMOS包括栅极和形成在N阱中的第一和第二P +掺杂区域，其中第一P +区域电连接到相应的位线。 存取PMOS包括栅极和形成在N阱内的第一和第二P +区，其中第一P +区电连接到编程/擦除PMOS的第二P +区，栅极电连接到相应的字 线。 控制栅极NMOS包括源极，漏极和栅极，其中源极和第三漏极以及p掺杂的阱电连接到相应的控制栅极线，并且栅极电连接到编程/擦除的栅极 PMOS，形成电池的浮动栅极。

    METHOD OF PROGRAMMING A SELECTED MEMORY CELL
    4.
    发明申请
    METHOD OF PROGRAMMING A SELECTED MEMORY CELL 有权
    编程选择的记忆细胞的方法

    公开(公告)号：US20080273392A1

    公开(公告)日：2008-11-06

    申请号：US12168858

    申请日：2008-07-07

    Applicant: Nirmal Ratnakumar ,  Venkatraman Prabhakar ,  David Kuan-Yu Liu

    Inventor： Nirmal Ratnakumar ,  Venkatraman Prabhakar ,  David Kuan-Yu Liu

    IPC: G11C16/06

    CPC classification number: G11C16/0441 ,  G11C16/3427 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558

    Abstract: A memory device including a plurality of memory cells, each with a control gate NMOS transistor sharing a floating gate with a program/erase PMOS transistor which is, in turn, connected in series with an access PMOS transistor. The memory cells are formed in a common N-Well formed in a P-substrate, the NMOS transistor being formed in a p-doped pocket or base. The program/erase PMOS includes a gate, and first and second P+ doped regions formed in the N-Well, wherein the first P+ region is electrically connected to a corresponding bit line. The access PMOS includes a gate, and first and second P+ regions formed within the N-Well, wherein the first P+ region is electrically connected to the second P+ region of the program/erase PMOS, and the gate is electrically connected to a corresponding word line. The control gate NMOS includes source, drain, and gate, wherein the source and third drain as well as the p-doped pocket are electrically connected to a corresponding control gate line, and the gate is electrically connected to the gate of the program/erase PMOS, forming floating gate of the cell.

    Abstract translation: 一种包括多个存储单元的存储器件，每个存储器单元具有与编程/擦除PMOS晶体管共享浮置栅极的控制栅极NMOS晶体管，该晶体管又与访问PMOS晶体管串联连接。 存储单元形成在形成在P基板中的公共N阱中，NMOS晶体管形成在p掺杂的凹穴或基底中。 编程/擦除PMOS包括栅极和形成在N阱中的第一和第二P +掺杂区域，其中第一P +区域电连接到相应的位线。 存取PMOS包括栅极和形成在N阱内的第一和第二P +区，其中第一P +区电连接到编程/擦除PMOS的第二P +区，栅极电连接到相应的字 线。 控制栅极NMOS包括源极，漏极和栅极，其中源极和第三漏极以及p掺杂的阱电连接到相应的控制栅极线，并且栅极电连接到编程/擦除的栅极 PMOS，形成电池的浮动栅极。

    Non-volatile latch with low voltage operation
    7.
    发明授权
    Non-volatile latch with low voltage operation 有权
    非易失性锁存器，低电压工作

    公开(公告)号：US07835179B1

    公开(公告)日：2010-11-16

    申请号：US12009710

    申请日：2008-01-22

    Applicant: Venkatraman Prabhakar

    Inventor： Venkatraman Prabhakar

    IPC: G11C11/34

    CPC classification number: G11C11/005 ,  G11C16/0441 ,  G11C16/28

    Abstract: Methods, circuits, devices, and/or arrangements for providing a non-volatile latch are disclosed. In one embodiment, a non-volatile latch can include: (i) a first non-volatile memory (NVM) cell coupled to a first supply, a first gate (e.g., a control gate), and an output node, where the first NVM cell is configured to be in a first state; and (ii) a second NVM cell coupled to a second supply, a second gate (e.g., another control gate), and the output node, where the second NVM cell is configured to be in a second state.

    Abstract translation: 公开了用于提供非易失性锁存器的方法，电路，装置和/或布置。 在一个实施例中，非易失性锁存器可以包括：（i）耦合到第一电源，第一门（例如，控制门）和输出节点的第一非易失性存储器（NVM）单元，其中第一 NVM单元被配置为处于第一状态; 以及（ii）耦合到第二电源的第二NVM单元，第二门（例如另一个控制门）和输出节点，其中第二NVM单元被配置为处于第二状态。

    1T SMART WRITE
    9.
    发明申请
    1T SMART WRITE 有权

    公开(公告)号：US20130083608A1

    公开(公告)日：2013-04-04

    申请号：US13248241

    申请日：2011-09-29

    Applicant: Venkatraman Prabhakar ,  Frederick Jenne

    Inventor： Venkatraman Prabhakar ,  Frederick Jenne

    IPC: G11C16/10

    CPC classification number: G11C16/16 ,  G11C11/5635 ,  G11C16/3409 ,  G11C16/3445

    Abstract: The threshold voltages of particular nonvolatile memory cells on a word line are selectively increased on a column by column (cell by cell) basis. A selective program is performed on some of the cells, and simultaneously a program inhibit on other of the cells, resulting in all of the cells having a threshold voltage that falls between a minimum acceptable value and a maximum acceptable value.

    Abstract translation: 字列上的特定非易失性存储单元的阈值电压在逐列（逐单元）的基础上选择性地增加。 对一些单元执行选择性程序，并且同时程序禁止其他单元，导致所有单元具有落在最小可接受值和最大可接受值之间的阈值电压。

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