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公开(公告)号：US10095657B2
公开(公告)日：2018-10-09
申请号：US15804002
申请日：2017-11-06
Applicant: WASEDA UNIVERSITY
Inventor： Hironori Kasahara , Keiji Kimura
Abstract: It is provided a processor system comprising at least one processor core provided on a semiconductor chip and including a processor, a memory and an accelerator. The memory includes an instruction area, a synchronization flag area and a data area. The accelerator starts, even if the processor is executing another processing, acceleration processing and executes the task in a case of confirming that a flag indicating that the processor has completed predetermined processing has been written into the synchronization flag area; and stores the data subjected to the acceleration processing into the data area, and further writes a flag indicating that the completion of the acceleration processing. The processor starts, even if the accelerator is executing another processing, the task corresponding to a flag in a case of confirming that the flag indicating the completion of the acceleration processing has been written into the synchronization flag area.
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公开(公告)号：US20180060275A1
公开(公告)日：2018-03-01
申请号：US15804002
申请日：2017-11-06
Applicant: WASEDA UNIVERSITY
Inventor： Hironori Kasahara , Keiji Kimura
CPC classification number: G06F15/76 , G06F9/3001 , G06F9/30087 , G06F9/38 , G06F9/3881 , G06F9/52 , G06F13/28 , G06F15/167
Abstract: It is provided a processor system comprising at least one processor core provided on a semiconductor chip and including a processor, a memory and an accelerator. The memory includes an instruction area, a synchronization flag area and a data area. The accelerator starts, even if the processor is executing another processing, acceleration processing and executes the task in a case of confirming that a flag indicating that the processor has completed predetermined processing has been written into the synchronization flag area; and stores the data subjected to the acceleration processing into the data area, and further writes a flag indicating that the completion of the acceleration processing. The processor starts, even if the accelerator is executing another processing, the task corresponding to a flag in a case of confirming that the flag indicating the completion of the acceleration processing has been written into the synchronization flag area.
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公开(公告)号：US20180181380A1
公开(公告)日：2018-06-28
申请号：US15856306
申请日：2017-12-28
Applicant: WASEDA UNIVERSITY
Inventor： Hironori Kasahara , Keiji Kimura , Dan Umeda , Hiroki Mikami
IPC: G06F8/41
Abstract: There is provided a parallel program generating method capable of generating a static scheduling enabled parallel program without undermining the possibility of extracting parallelism. The parallel program generating method executed by the parallelization compiling apparatus 100 includes a fusion step (FIG. 2/STEP026) of fusing, as a new task, a task group including a reference task as a task having a conditional branch, and subsequent tasks as tasks control dependent, extended-control dependent, or indirect control dependent on respective of all branch directions of the conditional branch included in the reference task.
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公开(公告)号：US10228923B2
公开(公告)日：2019-03-12
申请号：US15083502
申请日：2016-03-29
Applicant: DENSO CORPORATION , WASEDA UNIVERSITY
Inventor： Yoshihiro Yatou , Noriyuki Suzuki , Kenichi Mineda , Hironori Kasahara , Keiji Kimura , Hiroki Mikami , Dan Umeda
Abstract: A parallelization compiling method for generating a segmented program from a sequential program, in which multiple macro tasks are included and at least two of the macro tasks have a data dependency relationship with one another, includes determining an existence of invalidation information for invalidating at least a part of the data dependency relationship between the at least two of the plurality of macro tasks before compiling the sequential program into the segmented program, and generating the segmented program by compiling the sequential program into the segmented program with reference to a determination result of the existence of the invalidation information. When the invalidation information is determined to exist, the at least a part of the data dependency relationship is invalidated before the compiling of the sequential program into the segmented program.
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公开(公告)号：US09760355B2
公开(公告)日：2017-09-12
申请号：US14302886
申请日：2014-06-12
Applicant: DENSO CORPORATION , WASEDA UNIVERSITY
Inventor： Hiroshi Mori , Mitsuhiro Tani , Hironori Kasahara , Keiji Kimura , Dan Umeda , Akihiro Hayashi , Hiroki Mikami , Yohei Kanehagi
IPC: G06F9/45
Abstract: A parallelizing compile method includes, dividing a sequential program for an embedded system into multiple macro tasks, specifying (i) a starting end task and (ii) a termination end task, fusing (i) the starting end task, (ii) the termination end task, and (iii) a group of the multiple macro tasks, extracting a group of multiple new macro tasks from the multiple new macro tasks fused in the fusing based on a data dependency, performing a static scheduling assigning the multiple new macro tasks to the multiple processor units, so that the group of the multiple new macro tasks is parallelly executable by the multiple processor units, and generating a parallelizing program. In addition, a parallelizing compiler, a parallelizing compile apparatus and an onboard apparatus are provided.
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Patent Agency Ranking
公开(公告)号：US20140304491A1
公开(公告)日：2014-10-09
申请号：US14355339
申请日：2012-10-30
Applicant: WASEDA UNIVERSITY
Inventor： Hironori Kasahara , Keiji Kimura
CPC classification number: G06F15/76 , G06F9/3001 , G06F9/30087 , G06F9/38 , G06F9/3881 , G06F9/52 , G06F13/28 , G06F15/167
Abstract: It is provided a processor system comprising at least one processor core including a processor, a memory and an accelerator. The memory includes an instruction area, a synchronization flag area and a data area. The accelerator starts, even if the processor is executing another processing, acceleration processing and executes read instruction in a case where the read instruction is a flag checking instruction and a flag indicating the completion of predetermined processing has been written; and stores the data subjected to the acceleration processing after completion of the acceleration processing, and further writes a flag indicating the completion of the acceleration processing. The processor starts, even if the accelerator is executing another processing, read instruction corresponding to a flag in a case where the read instruction is the flag checking instruction and it is confirmed that the flag indicating the completion of the acceleration processing has been written.
Abstract translation: 提供了一种包括至少一个包括处理器，存储器和加速器的处理器核心的处理器系统。 存储器包括指令区，同步标记区和数据区。 加速器开始，即使处理器正在执行另一处理，加速处理，并且在读取指令是标志检查指令并且表示预定处理完成的标志已被写入的情况下执行读取指令; 并且在完成加速处理之后存储经受加速处理的数据，并且还写入指示加速处理完成的标志。 即使加速器正在执行另一处理，处理器启动，在读取指令是标志检查指令的情况下，读取与标志对应的指令，并且确认已经写入了表示加速处理完成的标志。
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公开(公告)号：US10698670B2
公开(公告)日：2020-06-30
申请号：US15856306
申请日：2017-12-28
Applicant: WASEDA UNIVERSITY
Inventor： Hironori Kasahara , Keiji Kimura , Dan Umeda , Hiroki Mikami
IPC: G06F8/41
Abstract: There is provided a parallel program generating method capable of generating a static scheduling enabled parallel program without undermining the possibility of extracting parallelism. The parallel program generating method executed by the parallelization compiling apparatus 100 includes a fusion step (FIG. 2/STEP026) of fusing, as a new task, a task group including a reference task as a task having a conditional branch, and subsequent tasks as tasks control dependent, extended-control dependent, or indirect control dependent on respective of all branch directions of the conditional branch included in the reference task.
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公开(公告)号：US09934012B2
公开(公告)日：2018-04-03
申请号：US15083526
申请日：2016-03-29
Applicant: DENSO CORPORATION , WASEDA UNIVERSITY
Inventor： Kazushi Nobuta , Noriyuki Suzuki , Hironori Kasahara , Keiji Kimura , Hiroki Mikami , Dan Umeda
IPC: G06F9/45
CPC classification number: G06F8/451
Abstract: A parallelization compiling method for generating a segmented program from a sequential program includes assigning macro tasks included in the sequential program to cores included in the multi-core processor in order to generate the segmented program, adding a new macro task to the sequential program or deleting one of the macro tasks from the sequential program, and compiling the sequential program into the segmented program in response to the adding of the new macro task under a condition that the macro tasks assigned to the cores do not migrate among the cores or compiling the sequential program into the segmented program in response to the deleting of the one of the macro tasks under a condition that remains of the macro tasks assigned to the cores do not migrate among the cores.
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公开(公告)号：US09846673B2
公开(公告)日：2017-12-19
申请号：US14355339
申请日：2012-10-30
Applicant: WASEDA UNIVERSITY
Inventor： Hironori Kasahara , Keiji Kimura
CPC classification number: G06F15/76 , G06F9/3001 , G06F9/30087 , G06F9/38 , G06F9/3881 , G06F9/52 , G06F13/28 , G06F15/167
Abstract: It is provided a processor system comprising at least one processor core including a processor, a memory and an accelerator. The memory includes an instruction area, a synchronization flag area and a data area. The accelerator starts, even if the processor is executing another processing, acceleration processing and executes read instruction in a case where the read instruction is a flag checking instruction and a flag indicating the completion of predetermined processing has been written; and stores the data subjected to the acceleration processing after completion of the acceleration processing, and further writes a flag indicating the completion of the acceleration processing. The processor starts, even if the accelerator is executing another processing, read instruction corresponding to a flag in a case where the read instruction is the flag checking instruction and it is confirmed that the flag indicating the completion of the acceleration processing has been written.
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公开(公告)号：US20150363230A1
公开(公告)日：2015-12-17
申请号：US14761789
申请日：2014-01-15
Applicant: WASEDA UNIVERSITY
Inventor： Hironori Kasahara , Keiji Kimura , Akihiro Hayashi , Hiroki Mikami , Yohei Kanehagi , Dan Umeda , Mitsuo Sawada
CPC classification number: G06F9/4881 , G06F8/456
Abstract: A method of extracting parallelism of an original program by a computer includes: a process of determining whether or not a plurality of macro tasks to be executed after a condition of one conditional branch included in the original program is satisfied are executable in parallel; and a process of copying the conditional branch regarding which the macro tasks are determined to be executable in parallel, to generate a plurality of conditional branches.
Abstract translation: 一种提取计算机原始程序的并行性的方法包括：执行在原始程序中包括的一个条件分支的条件被满足之后是否执行多个宏任务的处理，并行执行; 以及并行地确定宏任务被确定为可执行的条件分支的过程，以生成多个条件分支。
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