公开(公告)号：US20200258584A1

公开(公告)日：2020-08-13

申请号：US16863417

申请日：2020-04-30

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： Sahil Sharma ,  Phil Reusswig ,  Rohit Sehgal ,  Niles Yang

IPC: G11C16/32 ,  G11C16/28 ,  G11C11/56 ,  G11C7/06 ,  G11C16/04 ,  G11C7/10

Abstract: In one embodiment there is a method for calculating a timer at a storage device including a plurality of memory portions for storing data and a memory controller for performing operations on the memory portions, the method comprises receiving a request to perform an initial operation on a memory portion; determining an operational characteristic associated with the initial operation to be performed on the memory portion; and calculating an amount of time for a memory portion timer based on the operational characteristics before the initiation of the initial operation on the memory portion, wherein performance of a subsequent operation for another memory portion is delayed until the amount of time for the memory portion timer has elapsed since initiation of the operation on the memory portion.

公开(公告)号：US10515008B2

公开(公告)日：2019-12-24

申请号：US15793387

申请日：2017-10-25

Applicant: Western Digital Technologies, Inc.

Inventor： Rohit Sehgal ,  Nian Niles Yang

IPC: G06F12/00 ,  G06F12/02 ,  G06F3/06 ,  G11C16/34 ,  G11C11/56 ,  G11C16/10

Abstract: Blocks of memory cells may be selected for use based on one or more measured performance characteristics that may include, but are not limited to, programming time or fail bit count. Blocks may be placed into a single level cell (SLC) block pool and one or more multi-level cell (MLC) block pools based on measured performance characteristic(s). For example, blocks that have a better SLC performance may be placed into the SLC block pool. Blocks may be targeted for garbage collection based on one or more measured performance characteristics. For example, blocks within an SLC block pool may be targeted for garbage collection based on a performance ranking of the SLC blocks, blocks within an MLC block pool may be targeted for garbage collection based on a performance ranking of the MLC blocks. Thus, the better performing blocks may be used more frequently, thereby improving performance.

公开(公告)号：US11727984B2

公开(公告)日：2023-08-15

申请号：US17184536

申请日：2021-02-24

Applicant: Western Digital Technologies, Inc.

Inventor： Eran Sharon ,  Karin Inbar ,  Alexander Bazarsky ,  Dudy David Avraham ,  Rohit Sehgal ,  Gilad Koren

IPC: G11C16/26 ,  G11C11/56

CPC classification number: G11C11/5642 ,  G11C11/5671 ,  G11C16/26

Abstract: Data storage devices, such as solid state drives (SSDs), are disclosed. A read threshold calibration operation is utilized to generate a calibrated read threshold for one or more voltage states of a cell of a MLC memory. A single-level cell (SLC) read is then executed to sense the ratio of bit values at the read thresholds of the voltage states, where SLC read refers to reading at a single read threshold, rather than to the cell type. The sensing results in a binary page with certain statistics of 1's and 0's. The ratio of 1's (or 0's) in the binary page is used to determine a deviation from the expected ratio, where the deviation is used to adjust the calibrated read threshold to match the voltage states of the MLC memory.

公开(公告)号：US11334256B2

公开(公告)日：2022-05-17

申请号：US16780281

申请日：2020-02-03

Applicant: Western Digital Technologies, Inc.

Inventor： Sahil Sharma ,  Nian Niles Yang ,  Phil Reusswig ,  Rohit Sehgal ,  Piyush A. Dhotre

IPC: G06F3/06 ,  G11C11/409 ,  G06F11/07 ,  G11C11/408

Abstract: A storage system and method for boundary wordline data retention handling are provided. In one embodiment, the storage system includes a memory having a single-level cell (SLC) block and a multi-level cell (MLC) block. The system determines if the boundary wordline in the MLC block has a data retention problem (e.g., by determining how long it has been since the boundary wordline was programmed). To address the data retention problem, the storage system can copy data from a wordline in the SLC block that corresponds to the boundary wordline in the MLC block to a wordline in another SLC block prior to de-committing the data in the SLC block. Alternatively, the storage system can reprogram the data in the boundary wordline using a double fine programing technique.

公开(公告)号：US10996862B2

公开(公告)日：2021-05-04

申请号：US16443011

申请日：2019-06-17

Applicant: Western Digital Technologies, Inc.

Inventor： Phil Reusswig ,  Mohsen Purahmad ,  Sahil Sharma ,  Rohit Sehgal ,  Niles Yang

IPC: G06F3/06 ,  G11C16/34 ,  G11C16/32 ,  G11C16/26 ,  G11C16/04 ,  G06F12/02

Abstract: A data storage system performs operations including determining an endurance level of a block of memory cells; adjusting a read performance profile for the block of memory cells based on the determined endurance level; receiving a data read command specifying data to be read from a particular memory cell of the block of memory cells; and in response to the data read command, performing a read operation on the particular memory cell using the adjusted read performance profile.

公开(公告)号：US10896123B2

公开(公告)日：2021-01-19

申请号：US16218800

申请日：2018-12-13

Applicant: Western Digital Technologies, Inc.

Inventor： Nian Niles Yang ,  Sahil Sharma ,  Philip Reusswig ,  Rohit Sehgal

IPC: G06F12/02 ,  G11C16/34 ,  G11C29/42 ,  G06F11/10 ,  G11C29/52 ,  H04L1/20

Abstract: Techniques are described for performing a read scan process on a non-volatile memory system in order to determine memory blocks that may have a high bit error rate, where if such blocks are found they can be refreshed. Rather than work through the blocks of a memory system sequentially based on the physical block addresses, the memory system maintains a measure of data quality, such as an estimated or average bit error rate, for multi-block groups. For example, the groups can correspond to regions of memory die in the system. The groups are ranked by their data quality, with the groups being scanned in order of the data quality. The blocks within a group can also be ranked, based on factors such as the program/erase count.

公开(公告)号：US10770158B1

公开(公告)日：2020-09-08

申请号：US16412657

申请日：2019-05-15

Applicant: Western Digital Technologies, Inc.

Inventor： Mahim Gupta ,  Rohit Sehgal ,  Rohan Dhekane ,  Niles Yang ,  Aaron Lee

IPC: G11C16/06 ,  G11C16/34 ,  G11C29/00 ,  G11C29/24 ,  G11C29/44

Abstract: Detecting a faulty memory block. Various methods include: performing a read operation on a memory block of the memory array, the read operation generates a failed bit count; determining the failed bit count in above a value associated with an overall failed bit count; determining the failed bit count is above a threshold value; in response, performing a confirmation process on the memory block, the confirmation process defining a number of consecutive erase cycles and a level of an erase cycle, the confirmation process results in erase pass or erase fail; and marking the memory block for garbage collection in response to determining the confirmation process results in erase fail. Methods additionally include setting the level of the erase cycle by modifying at least one selected form the group comprising: an erase voltage parameter; an erase verify parameter; and a number of bits ignored during the erase cycle.

公开(公告)号：US20200226065A1

公开(公告)日：2020-07-16

申请号：US16244252

申请日：2019-01-10

Applicant: Western Digital Technologies, Inc.

Inventor： Niles Yang ,  Sahil Sharma ,  Rohit Sehgal ,  Phil Reusswig

IPC: G06F12/06 ,  G06F12/02 ,  G06F3/06

Abstract: Preparing a key block in a memory system. Various methods include: selecting a candidate key block of memory; checking a quality of the candidate key block using a word line of the candidate key block; altering operating parameters of the candidate key memory block; and registering the candidate key memory block as the key block. Where altering the operating parameters includes replacing a first set of parameters associated with the first memory block with a second set of parameters, where the first set of parameters includes a first erase parameter, a first program parameter, and a first read parameter, where the memory block operating in a normal block mode is accessed using the first set of parameters, and the second set of parameters includes a second erase parameter, a second program parameter, and a second read parameter, where the first memory block is accessed using the second set of parameters.

公开(公告)号：US10706936B1

公开(公告)日：2020-07-07

申请号：US16418319

申请日：2019-05-21

Applicant: Western Digital Technologies, Inc.

Inventor： Rohit Sehgal ,  Grishma Shah ,  Sahil Sharma ,  Phil Reusswig

IPC: G11C7/00 ,  G11C16/10 ,  G11C16/08 ,  G06F3/06 ,  G11C16/04

Abstract: In one embodiment, there is a system comprising a first group of blocks connected to a first address line, a second group of blocks connected to a second address line separate and distinct from the first address line, a host controller (or memory device) configured to: allocate a single open block to each of: the first group of blocks connected to the first address line that transmits an address signal generated by a first peripheral circuitry module, and the second group of blocks connected to the second address line that transmits an address signal generated by a second peripheral circuitry module; in response to receiving a first program request: program the open block in the first group of blocks connected to the first address line in response to a first program request in response to receiving a second program request separate and distinct from the first program request: forego programming any of the blocks in the first group of blocks connected to the first address line; and program one of the blocks in the second group of blocks connected to the second address line.

公开(公告)号：US10658045B1

公开(公告)日：2020-05-19

申请号：US16412859

申请日：2019-05-15

Applicant: Western Digital Technologies, Inc.

Inventor： Niles Yang ,  Sahil Sharma ,  Rohit Sehgal ,  Phil Reusswig

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/26

Abstract: A method for programming memory blocks in a memory system includes identifying, using at least one memory block characteristic, candidate memory blocks of the memory blocks in the memory system. The method also includes performing a pre-erase operation, using a pre-erase verify level, on the candidate memory blocks. The method also includes storing, on a pre-erase table, pre-erase information for each memory block of the candidate memory blocks. The method also includes identifying, using the pre-erase table, at least one memory block to be programmed. The method also includes programming the at least one memory block by performing a preprogram erase operation on the at least one memory block using the pre-erase verify level, and performing a write operation on the at least one memory block.