公开(公告)号：US07484972B1

公开(公告)日：2009-02-03

申请号：US11979399

申请日：2007-11-02

Applicant: Ming-Chou Kuo ,  Yi-Ching Lin

Inventor： Ming-Chou Kuo ,  Yi-Ching Lin

IPC: H01R13/44

CPC classification number: H01R35/04 ,  H01R13/44 ,  H01R13/60

Abstract: A rotatable plug includes a plug body, a rotatable base and at least two conductive terminals. One end of the plug body has an accommodating space. The plug body is provided with a penetrating hole to make the plug body to form a hollow annular body. The rotatable base is rotatably provided in the accommodating space of the plug body. The two conductive terminals are provided on the rotatable base. The two conductive terminals rotate together with the rotatable base to the outside of the plug body or are accommodated in the plug body. Via this arrangement, the conductive terminals can be avoided from getting inclined or suffering damage by the impact or compression during transportation. Further, it is convenient for the user to put his/her finger in the hollow annular body to pull out the plug.

Abstract translation: 可旋转插头包括插头主体，可旋转底座和至少两个导电端子。 插头体的一端具有容纳空间。 塞体设置有穿孔，以使塞体形成中空的环形体。 可旋转底座可旋转地设置在塞体的容纳空间中。 两个导电端子设置在可旋转底座上。 两个导电端子与可旋转基座一起旋转到插塞体的外部，或者容纳在插头体中。 通过这种布置，可以避免导电端子在运输过程中受冲击或压缩而变得倾斜或遭受损坏。 此外，用户方便地将他/她的手指放在中空的环形体中以拉出插头。

公开(公告)号：US07382012B2

公开(公告)日：2008-06-03

申请号：US11361330

申请日：2006-02-24

Applicant: Kuo-Chi Tu ,  Chun-Yao Chen ,  Yi-Ching Lin

Inventor： Kuo-Chi Tu ,  Chun-Yao Chen ,  Yi-Ching Lin

IPC: H01L27/108 ,  H01L21/20 ,  G11C11/00

CPC classification number: H01L28/40 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/56

Abstract: A memory device having improved sensing speed and reliability and a method of forming the same are provided. The memory device includes a first dielectric layer having a low k value over a semiconductor substrate, a second dielectric layer having a second k value over the first dielectric layer, and a capacitor formed in the second dielectric layer wherein the capacitor comprises a cup region at least partially filled by the third dielectric layer. The memory device further includes a third dielectric layer over the second dielectric layer and a bitline over the third dielectric layer. The bitline is electrically coupled to the capacitor. A void having great dimensions is preferably formed in the cup region of the capacitor.

Abstract translation: 提供了具有改进的感测速度和可靠性的记忆装置及其形成方法。 存储器件包括在半导体衬底上具有低k值的第一电介质层，在第一介电层上具有第二k值的第二电介质层和形成在第二电介质层中的电容器，其中电容器包括位于 最少部分地被第三介电层填充。 存储器件还包括第二电介质层上的第三电介质层和第三电介质层上的位线。 位线电耦合到电容器。 优选地，在电容器的杯区域中形成具有大尺寸的空隙。

公开(公告)号：US20080124875A1

公开(公告)日：2008-05-29

申请号：US11592204

申请日：2006-11-03

Applicant: Ken Liao ,  Kuo-Hua Pan ,  Yun-Hsiu Chen ,  Syun-Ming Jang ,  Yi-Ching Lin

Inventor： Ken Liao ,  Kuo-Hua Pan ,  Yun-Hsiu Chen ,  Syun-Ming Jang ,  Yi-Ching Lin

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/266 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636

Abstract: A method for forming a strained channel in a semiconductor device is provided, comprises providing of a transistor comprising a gate stack exposed with a gate electrode on a semiconductor substrate, a pair of source/drain regions in the substrate on opposite sides of the gate stack and a pair of spacers on opposing sidewalls of the gate stack. A passivation layer is formed to cover the gate electrode and spacers of the transistor. A passivation layer is formed to cover the gate electrode and the spacers. A recess region is formed in each of the source/drain regions, wherein an edge of the recess region aligns to an outer edge of the spacers. The recess regions are filled with a strain-exerting material, thereby forming a strained channel region in the semiconductor substrate between the source/drain regions.

Abstract translation: 提供了一种在半导体器件中形成应变通道的方法，包括提供晶体管，其包括在半导体衬底上暴露有栅极电极的栅极堆叠，在栅极堆叠的相对侧的衬底中的一对源极/漏极区域 以及在栅极堆叠的相对的侧壁上的一对隔板。 形成钝化层以覆盖晶体管的栅电极和间隔物。 形成钝化层以覆盖栅电极和间隔物。 在每个源极/漏极区域中形成凹陷区域，其中凹部区域的边缘与间隔物的外边缘对准。 用应变施加材料填充凹陷区域，从而在源极/漏极区域之间的半导体衬底中形成应变通道区域。

公开(公告)号：US20070267674A1

公开(公告)日：2007-11-22

申请号：US11437673

申请日：2006-05-22

Applicant: Yi-Ching Lin ,  Chun-Yao Chen ,  Chen-Jong Wang ,  Shou-Gwo Wuu ,  Chung S. Wang ,  Chien-Hua Huang ,  Kun-Lung Chen ,  Ping Yang

Inventor： Yi-Ching Lin ,  Chun-Yao Chen ,  Chen-Jong Wang ,  Shou-Gwo Wuu ,  Chung S. Wang ,  Chien-Hua Huang ,  Kun-Lung Chen ,  Ping Yang

IPC: H01L29/94

CPC classification number: H01L27/10897 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10894

Abstract: Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.

Abstract translation: 嵌入式记忆 这些器件包括衬底，第一介电层，第二电介质层，第三电介质层和多个电容器。 衬底包括晶体管。 第一介电层，嵌入电连接其中的晶体管的第一和第二导电插塞覆盖在基板上。 包括暴露第一导电插塞的多个电容器开口的第二电介质层覆盖在第一电介质层上。 电容器包括分别设置在电容器开口中的多个底板，电连接第一导电插塞，分别覆盖在底板上的多个电容器电介质层，以及顶板，包括覆盖电容器电介质的顶板开口 层。 顶板开口暴露第二电介质层，并且顶板由电容器共享。

公开(公告)号：US5175126A

公开(公告)日：1992-12-29

申请号：US635686

申请日：1990-12-27

Applicant: Huei-Min Ho ,  Yi-Ching Lin

Inventor： Huei-Min Ho ,  Yi-Ching Lin

IPC: H01L21/768

CPC classification number: H01L21/76831 ,  H01L21/76843 ,  H01L21/76856

Abstract: Two methods for substantially improving the integrity of a TiN barrier layer are disclosed. The first method allows an atmospheric anneal in a conventional semiconductor furnace. The atmospheric anneal substantially seals the exposed TiN surface preventing subsequent metal layers from migrating through the barrier layer. The second method involves a reaction within a plasma reactor using a plasma gas. The plasma gas reacts with titanium within the TiN film to form a desired titanium compound. The gas is adsorbed onto the TiN grains at the grain boundaries within the TiN film thus filling the grain boundaries and thus substantially preventing subsequent metal layers from migrating though the TiN barrier layer. The second method allows the deposition of TiN, the plasma reaction, and subsequent metal depositions to take place on the same equipment using the same evacuation cycle.

Abstract translation: 公开了用于显着改善TiN阻挡层完整性的两种方法。 第一种方法允许常规半导体炉中的大气退火。 大气退火基本上密封暴露的TiN表面，防止随后的金属层迁移通过阻挡层。 第二种方法涉及使用等离子体气体的等离子体反应器内的反应。 等离子体气体与TiN膜内的钛反应形成所需的钛化合物。 气体被吸附到TiN膜内的晶界处的TiN晶粒上，从而填充晶界，从而基本上防止随后的金属层通过TiN势垒层迁移。 第二种方法允许沉积TiN，等离子体反应和随后的金属沉积在相同的设备上使用相同的抽空循环进行。

公开(公告)号：US08148223B2

公开(公告)日：2012-04-03

申请号：US11437673

申请日：2006-05-22

Applicant: Yi-Ching Lin ,  Chun-Yao Chen ,  Chen-Jong Wang ,  Shou-Gwo Wuu ,  Chung S. Wang ,  Chien-Hua Huang ,  Kun-Lung Chen ,  Ping Yang

Inventor： Yi-Ching Lin ,  Chun-Yao Chen ,  Chen-Jong Wang ,  Shou-Gwo Wuu ,  Chung S. Wang ,  Chien-Hua Huang ,  Kun-Lung Chen ,  Ping Yang

IPC: H01L21/8242

CPC classification number: H01L27/10897 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10894

Abstract: Embedded memories. The devices include a substrate, a first dielectric layer, a second dielectric layer, a third dielectric layer, and a plurality of capacitors. The substrate comprises transistors. The first dielectric layer, embedding first and second conductive plugs electrically connecting the transistors therein, overlies the substrate. The second dielectric layer, comprising a plurality of capacitor openings exposing the first conductive plugs, overlies the first dielectric layer. The capacitors comprise a plurality of bottom plates, respectively disposed in the capacitor openings, electrically connecting the first conductive plugs, a plurality of capacitor dielectric layers respectively overlying the bottom plates, and a top plate, comprising a top plate opening, overlying the capacitor dielectric layers. The top plate opening exposes the second dielectric layer, and the top plate is shared by the capacitors.

Abstract translation: 嵌入式记忆 这些器件包括衬底，第一介电层，第二电介质层，第三电介质层和多个电容器。 衬底包括晶体管。 第一介电层，嵌入电连接其中的晶体管的第一和第二导电插塞覆盖在基板上。 包括暴露第一导电插塞的多个电容器开口的第二电介质层覆盖在第一电介质层上。 电容器包括分别设置在电容器开口中的多个底板，电连接第一导电插塞，分别覆盖在底板上的多个电容器电介质层，以及顶板，包括覆盖电容器电介质的顶板开口 层。 顶板开口暴露第二电介质层，并且顶板由电容器共享。

公开(公告)号：US07754571B2

公开(公告)日：2010-07-13

申请号：US11592204

申请日：2006-11-03

Applicant: Ken Liao ,  Kuo-Hua Pan ,  Yun-Hsiu Chen ,  Syun-Ming Jang ,  Yi-Ching Lin

Inventor： Ken Liao ,  Kuo-Hua Pan ,  Yun-Hsiu Chen ,  Syun-Ming Jang ,  Yi-Ching Lin

IPC: H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/266 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636

Abstract: A method for forming a strained channel in a semiconductor device is provided, comprises providing of a transistor comprising a gate stack exposed with a gate electrode on a semiconductor substrate, a pair of source/drain regions in the substrate on opposite sides of the gate stack and a pair of spacers on opposing sidewalls of the gate stack. A passivation layer is formed to cover the gate electrode and spacers of the transistor. A passivation layer is formed to cover the gate electrode and the spacers. A recess region is formed in each of the source/drain regions, wherein an edge of the recess region aligns to an outer edge of the spacers. The recess regions are filled with a strain-exerting material, thereby forming a strained channel region in the semiconductor substrate between the source/drain regions.

Abstract translation: 提供了一种在半导体器件中形成应变通道的方法，包括提供晶体管，该晶体管包括在半导体衬底上暴露有栅电极的栅极叠层，在栅极叠层的相对侧上的衬底中的一对源极/漏极区域 以及在栅极堆叠的相对的侧壁上的一对隔板。 形成钝化层以覆盖晶体管的栅电极和间隔物。 形成钝化层以覆盖栅电极和间隔物。 在每个源极/漏极区域中形成凹陷区域，其中凹部区域的边缘与间隔物的外边缘对准。 用应变施加材料填充凹陷区域，从而在源极/漏极区域之间的半导体衬底中形成应变通道区域。

公开(公告)号：US07467971B2

公开(公告)日：2008-12-23

申请号：US11637872

申请日：2006-12-13

Applicant: Yi-Ching Lin ,  Ming-Chou Kuo

Inventor： Yi-Ching Lin ,  Ming-Chou Kuo

IPC: H01R13/72

CPC classification number: H01R13/60 ,  H01R13/652 ,  H01R13/72 ,  H01R13/73 ,  H01R24/30 ,  H01R24/78 ,  H01R25/00 ,  H01R2103/00

Abstract: A retractable extension socket includes an socket body, a fixing structure, a receiving structure, a conducting wire and a plug. The fixing structure and the receiving structure are disposed on the socket body. One end of the conducting wire is connected to the socket body. The plug is connected to the other end of the conducting wire. Thus, a retractable extension socket is formed. The retractable extension socket can be used as an extension socket. In addition, by winding the cable into the socket body and attaching the plug into the fixing structure, the retractable extension socket can be used as a single plug. Furthermore, the plug can be collected into the receiving structure in order that it can be carried around easily.

公开(公告)号：US07422437B1

公开(公告)日：2008-09-09

申请号：US11829480

申请日：2007-07-27

Applicant: Yi-Ching Lin ,  Ming-Chou Kuo ,  Jung-Hui Hsu

Inventor： Yi-Ching Lin ,  Ming-Chou Kuo ,  Jung-Hui Hsu

IPC: H01R39/00

CPC classification number: H01R31/06 ,  H01R35/04

Abstract: A portable adapter includes a first body; a second body; a pivoting unit, mounted between the first body and the second body; a power input, mounted on the first body; a power output, mounted on the first body near to the pivoting unit; and at least one connector, mounted on the second body. The pivoting unit unfolds the first body and the second body in a manner such that the power output is partially hidden between the first body and the second body. The foldable structure of the portable adapter has a reduced volume and the power output is partially hidden during travel. When in use with a laptop, the first body and the second body unfold to an angle of 90 degrees relative to each other by means of the pivoting unit, so that the connector can be plugged with an electronic device.

Abstract translation: 便携式适配器包括第一主体; 第二个身体 枢转单元，安装在所述第一主体和所述第二主体之间; 电源输入，安装在第一机身上; 功率输出，安装在靠近枢转单元的第一主体上; 以及安装在第二主体上的至少一个连接器。 枢转单元以使得功率输出部分地隐藏在第一主体和第二主体之间的方式展开第一主体和第二主体。 便携式适配器的可折叠结构具有减小的体积，并且在行驶期间功率输出部分隐藏。 当与膝上型计算机一起使用时，第一主体和第二主体通过枢转单元相对于彼此展开成90度的角度，使得连接器可以用电子装置插入。

公开(公告)号：US07374425B1

公开(公告)日：2008-05-20

申请号：US11797780

申请日：2007-05-08

Applicant: Ming-Chou Kuo ,  Yi-Ching Lin ,  Jung-Hui Hsu

Inventor： Ming-Chou Kuo ,  Yi-Ching Lin ,  Jung-Hui Hsu

IPC: H01R25/00

CPC classification number: H01R25/003

Abstract: A foldable power supply device includes a first socket, a second socket, and a pivoting unit. The first socket has multiple sets of first plugging holes and first conductive plates. The second socket has multiple sets of second plugging holes and second conductive plates. The pivoting unit is located between the first socket and the second socket. The direction of the rotation shaft of the pivoting unit is not parallel to the plugging direction of the first plugging holes and the second plugging holes. Thereby, the foldable power supply device can be opened into a block type to lower its height and be used as a multi-hole type. Alternatively, the device can also be folded to become a vertical type so that one side of the device can align with the wall, and the plugs or the transformers can be plugged into the device in two face-to-face directions.

Abstract translation: 可折叠供电装置包括第一插座，第二插座和枢转单元。 第一插座具有多组第一插孔和第一导电板。 第二插座具有多组第二插孔和第二导电板。 枢转单元位于第一插座和第二插座之间。 枢转单元的旋转轴的方向不平行于第一堵塞孔和第二堵塞孔的堵塞方向。 因此，可折叠供电装置可以被打开成块状以降低其高度并用作多孔类型。 或者，该装置也可以折叠成垂直型，使得装置的一侧可以与壁对准，并且插头或变压器可以以两个面对面的方向插入装置。