公开(公告)号：US20180096969A1

公开(公告)日：2018-04-05

申请号：US15726905

申请日：2017-10-06

Applicant: ams AG

Inventor： Jochen KRAFT ,  Martin SCHREMS ,  Franz SCHRANK

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L21/683 ,  H01L23/498 ,  H01L23/48 ,  H01L23/538 ,  H01L23/14 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L25/0655 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/85 ,  H01L24/92 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13024 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24146 ,  H01L2224/24147 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45099 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82 ,  H01L2224/82005 ,  H01L2224/82031 ,  H01L2224/83005 ,  H01L2224/85 ,  H01L2224/85005 ,  H01L2224/9222 ,  H01L2224/92242 ,  H01L2224/92244 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/207

Abstract: The method of producing an interposer-chip-arrangement, comprises providing an interposer (1) with an integrated circuit (25), arranging a dielectric layer (2) with metal layers embedded in the dielectric layer above a main surface (10) of the interposer, connecting the integrated circuit with at least one of the metal layers, forming an interconnection (7) through the interposer, the interconnection contacting one of the metal layers, arranging a further dielectric layer (3) above a further main surface (11) of the interposer opposite the main surface and arranging a further metal layer in or on the further dielectric layer, the further metal layer being connected with the interconnection, arranging a chip provided with at least one contact pad at the main surface or at the further main surface, and electrically conductively connecting the contact pad with the interconnection.

公开(公告)号：US20160035929A1

公开(公告)日：2016-02-04

申请号：US14777484

申请日：2014-03-11

Applicant: AMS AG

Inventor： Jordi TEVA ,  Frederic ROGER ,  Ewald STUECKLER ,  Stefan JESSENIG ,  Rainer MINIXHOFER ,  Ewald WACHMANN ,  Martin SCHREMS ,  Guenther KOPPITSCH

IPC: H01L31/107 ,  H01L31/18 ,  H01L31/0368 ,  H01L31/0224 ,  H01L31/0352

CPC classification number: H01L31/107 ,  H01L31/022408 ,  H01L31/03529 ,  H01L31/03682 ,  H01L31/182 ,  Y02E10/50

Abstract: The lateral single-photon avalanche diode comprises a semiconductor body comprising a semiconductor material of a first type of electric conductivity, a trench in the semiconductor body, and anode and cathode terminals. A junction region of the first type of electric conductivity is located near the sidewall of the trench, and the electric conductivity is higher in the junction region than at a farther distance from the sidewall. A semiconductor layer of an opposite second type of electric conductivity is arranged at the sidewall of the trench adjacent to the junction region. The anode and cathode terminals are electrically connected with the semiconductor layer and with the junction region, respectively. The junction region may be formed by a sidewall implantation.

Abstract translation: 横向单光子雪崩二极管包括半导体本体，其包括第一导电类型的半导体材料，半导体主体中的沟槽以及阳极和阴极端子。 第一类电导率的结区域位于沟槽的侧壁附近，并且在结区域中的电导率高于距离侧壁更远的距离。 相邻的第二导电类型的半导体层被布置在与结区相邻的沟槽的侧壁处。 阳极和阴极端子分别与半导体层和结区域电连接。 接合区域可以通过侧壁注入形成。

公开(公告)号：US20190312076A1

公开(公告)日：2019-10-10

申请号：US16309226

申请日：2017-06-13

Applicant: ams AG

Inventor： Martin SCHREMS ,  Thomas STOCKMEIER

IPC: H01L27/146 ,  G02B5/20

Abstract: The system-on-chip camera comprises a semiconductor body (1) with an integrated circuit (40), a sensor substrate (2), sensor elements (3) arranged in the sensor substrate according to an array of pixels, a light sensor (4) in the sensor substrate apart from the sensor elements, and a lens or an array of lenses (15) on a surface of incidence (30). Filter elements (11, 12, 13), which may especially be interference filters for red, green or blue, are arranged between the sensor elements and the surface of incidence.

公开(公告)号：US20170309665A1

公开(公告)日：2017-10-26

申请号：US15528089

申请日：2015-11-09

Applicant: ams AG

Inventor： Joerg SIEGERT ,  Franz SCHRANK ,  Martin SCHREMS

IPC: H01L27/146

CPC classification number: H01L27/14623 ,  H01L23/481 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/14685

Abstract: A photosensor (2) is arranged in a semiconductor substrate (1) at a main surface (10), a dielectric layer (4) is arranged on or above the main surface, the dielectric layer including a metal layer (6) electrically connected with the photosensor, and an aperture layer (16) formed from an opaque or semitransparent material is arranged on or above the dielectric layer. The aperture layer is provided with an array of transparent aperture zones (18) above the photosensor, each of the aperture zones penetrating the aperture layer.

公开(公告)号：US20170179056A1

公开(公告)日：2017-06-22

申请号：US15118469

申请日：2015-02-09

Applicant: Ams AG

Inventor： Martin SCHREMS ,  Bernhard STERING ,  Harald ETSCHMAIER

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/485

CPC classification number: H01L24/11 ,  H01L23/31 ,  H01L23/3157 ,  H01L23/481 ,  H01L23/485 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02125 ,  H01L2224/03001 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/05555 ,  H01L2224/05563 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/05576 ,  H01L2224/05599 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The semiconductor device comprises a semiconductor substrate (1) with a main surface (10) and a further main surface (11) opposite the main surface, a TSV (3) penetrating the substrate from the main surface to the further main surface, a metallization (13) of the TSV, an under-bump metallization (5) and a bump contact (6) at least partially covering the TSV at the further main surface. The TSV (3) comprises a cavity (15), which may be filled with a gas or liquid. An opening (15′) of the cavity is provided to expose the cavity to the environment.

公开(公告)号：US20170018518A1

公开(公告)日：2017-01-19

申请号：US15283189

申请日：2016-09-30

Applicant: ams AG

Inventor： Cathal CASSIDY ,  Martin SCHREMS ,  Franz SCHRANK

IPC: H01L23/00

CPC classification number: H01L23/5226 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53295 ,  H01L23/552 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/10125 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13025 ,  H01L2224/13027 ,  H01L2224/13028 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/13561 ,  H01L2224/1357 ,  H01L2224/136 ,  H01L2224/16106 ,  H01L2224/1613 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/30101 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A semiconductor substrate is provided with a through-substrate via comprising a metallization and an opening. A solder ball is placed on the opening. A reflow of the solder ball is performed in such a way that the solder ball closes the through-substrate via and leaves a void in the through-substrate via.

Abstract translation: 半导体衬底设置有包括金属化和开口的贯穿衬底通孔。 焊球放置在开口处。 焊球的回流以这样的方式进行，使得焊球闭合贯穿基板通孔，并在通孔中留下空隙。

公开(公告)号：US20200313031A1

公开(公告)日：2020-10-01

申请号：US16756025

申请日：2018-10-15

Applicant: ams AG

Inventor： Gregor TOSCHKOFF ,  Thomas BODNER ,  Franz SCHRANK ,  Miklos LABODI ,  Joerg SIEGERT ,  Martin SCHREMS

IPC: H01L31/18 ,  G01J1/04 ,  G01J1/02 ,  H01L31/0216 ,  H01L31/02 ,  H01L31/0203

Abstract: A method for manufacturing an optical sensor is provided. The method comprises providing an optical sensor arrangement which comprises at least two optical sensor elements on a carrier, where the optical sensor arrangement comprises a light entrance surface at the side of the optical sensor elements facing away from the carrier. The method further comprises forming a trench between two optical sensor elements in a vertical direction which is perpendicular to the main plane of extension of the carrier, where the trench extends from the light entrance surface of the sensor arrangement at least to the carrier. Moreover, the method comprises coating the trench with an opaque material, forming electrical contacts for the at least two optical sensor elements on a back side of the carrier facing away from the optical sensor elements, and forming at least one optical sensor by dicing the optical sensor arrangement along the trench. Each optical sensor comprises an optical sensor element, and the light entrance surface is free of electrical contacts and at least partially free of the opaque material above the optical sensor elements. Furthermore, an optical sensor is provided.

公开(公告)号：US20170062277A1

公开(公告)日：2017-03-02

申请号：US15118836

申请日：2015-02-09

Applicant: ams AG

Inventor： Martin SCHREMS ,  Bernhard STERING ,  Franz SCHRANK

IPC: H01L21/78 ,  H01L21/768 ,  H01L23/00 ,  H01L21/683

CPC classification number: H01L21/78 ,  H01L21/6835 ,  H01L21/76898 ,  H01L24/11 ,  H01L2224/02372 ,  H01L2224/05569

Abstract: The dicing method comprises the steps of providing a substrate (1) of semiconductor material, the substrate having a main surface (10), where integrated components (3) of chips (13) are arranged, and a rear surface (11) opposite the main surface, fastening a first handling wafer above the main surface, thinning the substrate at the rear surface, and forming trenches (20) penetrating the substrate and separating the chips by a single etching step after the substrate has been thinned.

Abstract translation: 切割方法包括以下步骤：提供半导体材料的基板（1），所述基板具有主表面（10），其中布置有芯片（13）的集成部件（3）和与所述芯片（13）相对的后表面 主表面，紧固在主表面上方的第一处理晶片，使后表面上的基板变薄，并且在基板变薄之后，形成穿透基板的沟槽（20）并通过单个蚀刻步骤分离芯片。

公开(公告)号：US20160306042A1

公开(公告)日：2016-10-20

申请号：US15101893

申请日：2014-12-03

Applicant: AMS AG

Inventor： Franz SCHRANK ,  Eugene G. DIERSCHKE ,  Martin SCHREMS

IPC: G01S17/02 ,  H01L27/144 ,  H01L25/16 ,  H01L31/0216 ,  H01L31/0232 ,  H01L31/173 ,  H01L31/02

CPC classification number: G01S17/026 ,  G01S7/4813 ,  H01L25/167 ,  H01L27/1443 ,  H01L31/02005 ,  H01L31/0203 ,  H01L31/02164 ,  H01L31/02165 ,  H01L31/02325 ,  H01L31/02327 ,  H01L31/125 ,  H01L31/14 ,  H01L31/167 ,  H01L31/173 ,  H01L33/483 ,  H01L33/52 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2924/0002 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An optical sensor arrangement, in particular an optical proximity sensor arrangement comprises a three-dimensional integrated circuit further comprising a first layer comprising a light-emitting device, a second layer comprising a light-detector and a driver circuit. The driver circuit is electrically connected to the light-emitting device and to the light-detector to control the operation of the light-emitting device and the light-detector. A mold layer comprising a first light-barrier between the light-emitting device and the light-detector configured to block light from being transmitted directly from the light-emitting device to the light-detector.

Abstract translation: 光学传感器装置，特别是光学接近传感器装置包括三维集成电路，其还包括包括发光器件的第一层，包括光检测器和驱动器电路的第二层。 驱动电路电连接到发光装置和光检测器，以控制发光装置和光检测器的操作。 一种模制层，包括在所述发光装置和所述光检测器之间的第一光阻，所述光检测器被配置为阻止光直接从所述发光装置传输到所述光检测器。

公开(公告)号：US20150348817A1

公开(公告)日：2015-12-03

申请号：US14654471

申请日：2013-12-19

Applicant: AMS AG

Inventor： Thomas BODNER ,  Joerg SIEGERT ,  Martin SCHREMS

IPC: H01L21/683

CPC classification number: H01L21/6835 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  Y10T156/10 ,  Y10T156/1111

Abstract: A relief structure is formed on a surface of a carrier provided for accommodating a wafer, which is fastened to the carrier by a removable adhesive contacting the carrier. The relief structure, which may be spatially confined to the centre of the carrier, reduces the strength of adhesion between the wafer and the carrier. If the adhesive is appropriately selected and maintains the connection between the wafer and the carrier at elevated temperatures, further process steps can be performed at temperatures of typically 300° C. or more. The subsequent mechanical separation of the adhesive joint is facilitated by the relief structure on the carrier.

Abstract translation: 浮雕结构形成在用于容纳晶片的载体的表面上，该晶片通过与载体接触的可移除的粘合剂固定到载体上。 可以在空间上限制在载体的中心的浮雕结构降低了晶片和载体之间的粘合强度。 如果适当地选择粘合剂并且在升高的温度下维持晶片和载体之间的连接，则可以在通常为300℃或更高的温度下进行进一步的工艺步骤。 粘合剂接头随后的机械分离由载体上的浮雕结构促进。