公开(公告)号：US20190187254A1

公开(公告)日：2019-06-20

申请号：US16326755

申请日：2017-08-24

Applicant: ams AG

Inventor： Robert KAPPEL ,  Mario MANNINGER ,  Todd BISHOP

IPC: G01S7/481 ,  G01S17/08 ,  G01S7/48

CPC classification number: G01S7/4813 ,  G01S7/4808 ,  G01S7/497 ,  G01S17/08

Abstract: An optical sensor module for time-of-flight measurement comprises an optical emitter, a main detector and a reference detector which are arranged in or on a carrier. An opaque housing of the optical sensor module has a first chamber and a second chamber which are separated by a light barrier. The housing has a cover section and is arranged on the carrier such that the optical emitter is located inside the first chamber, the main detector is located inside the second chamber and the reference detector is located outside the first chamber. Furthermore, a main surface of the cover section is positioned opposite the carrier. The optical emitter is arranged and configured to emit light through a first aperture in the cover section, and the main detector is arranged and configured to detect light entering the second chamber through a second aperture in the cover section. A reference path is established between the optical emitter and the reference detector inside the optical sensor module, and confined by the main surface of the cover section and the carrier. Additionally, a method for manufacturing an optical sensor module for time-of-flight measurement is presented.

公开(公告)号：US20220026535A1

公开(公告)日：2022-01-27

申请号：US17277006

申请日：2019-09-12

Applicant: ams AG

Inventor： Robert KAPPEL

IPC: G01S7/481 ,  G01S7/4863 ,  G01S17/89

Abstract: A sensor device is provided and includes an array of photodetectors. A readout circuit is connected to the array of photodetectors and provides dedicated readout paths for each photodetector in the array, respectively. Further, the readout circuit includes at least one control terminal. An array of time-to-digital converters is electrically connected to converter output terminals of the readout circuit. Depending on a control signal to be applied at the at least one control terminal , the readout circuit is arranged to electrically connect through the readout paths of photodetectors of a first subarray (11) to the converter output terminals of the readout circuit, respectively, thereby rendering the photodetectors of the first subarray active and photodetectors of a second subarray inactive.

公开(公告)号：US20210203221A1

公开(公告)日：2021-07-01

申请号：US17055903

申请日：2019-04-05

Applicant: ams AG

Inventor： Nenad LILIC ,  Robert KAPPEL ,  Georg RÖHRER

IPC: H02M3/07 ,  H01L27/092 ,  H01L29/94

Abstract: A charge pump circuit arrangement includes a multitude of capacitors of a first and a second group controlled by non-overlapping clock pulses. The capacitors are partly realized in a semiconductor substrate including a deep well doping region and a high voltage doping region surrounded by the deep well doping region. Switches are connected to a pair of capacitors to control the deep well doping regions with signals in phase with the corresponding clock signal.