公开(公告)号：US11527643B2

公开(公告)日：2022-12-13

申请号：US17342567

申请日：2021-06-09

Applicant: uPI Semiconductor Corp.

Inventor： Nobuyuki Shirai ,  Chun-Hsu Chang ,  Ming-Hung Chou

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/033 ,  H01L29/66

Abstract: Provided is a method of forming a trench gate MOSFET. A hard mask layer is formed on a substrate. The substrate is partially removed by using the hard mask layer as a mask, so as to form a trench in the substrate. A first insulating layer and a first conductive layer are formed in the lower portion of the trench. A sacrificial layer is formed on the side surface of the upper portion of the trench, and the sacrificial layer is connected to the hard mask layer. An interlayer insulating layer is formed on the first conductive layer by a thermal oxidation process when the sacrificial layer and the hard mask layer are present. A second insulating layer and a second conductive layer are formed in the upper portion of the trench. A trench gate MOSFET is further provided.

公开(公告)号：US20210296493A1

公开(公告)日：2021-09-23

申请号：US17342567

申请日：2021-06-09

Applicant: uPI Semiconductor Corp.

Inventor： Nobuyuki Shirai ,  Chun-Hsu Chang ,  Ming-Hung Chou

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/033 ,  H01L29/66

Abstract: Provided is a method of forming a trench gate MOSFET. A hard mask layer is formed on a substrate. The substrate is partially removed by using the hard mask layer as a mask, so as to form a trench in the substrate. A first insulating layer and a first conductive layer are formed in the lower portion of the trench. A sacrificial layer is formed on the side surface of the upper portion of the trench, and the sacrificial layer is connected to the hard mask layer. An interlayer insulating layer is formed on the first conductive layer by a thermal oxidation process when the sacrificial layer and the hard mask layer are present. A second insulating layer and a second conductive layer are formed in the upper portion of the trench. A trench gate MOSFET is further provided.

公开(公告)号：US11075296B2

公开(公告)日：2021-07-27

申请号：US16412427

申请日：2019-05-15

Applicant: uPI Semiconductor Corp.

Inventor： Nobuyuki Shirai ,  Chun-Hsu Chang ,  Ming-Hung Chou

IPC: H01L29/78 ,  H01L29/423 ,  H01L21/033 ,  H01L29/66

Abstract: Provided is a method of forming a trench gate MOSFET. A hard mask layer is formed on a substrate. The substrate is partially removed by using the hard mask layer as a mask, so as to form a trench in the substrate. A first insulating layer and a first conductive layer are formed in the lower portion of the trench. A sacrificial layer is formed on the side surface of the upper portion of the trench, and the sacrificial layer is connected to the hard mask layer. An interlayer insulating layer is formed on the first conductive layer by a thermal oxidation process when the sacrificial layer and the hard mask layer are present. A second insulating layer and a second conductive layer are formed in the upper portion of the trench. A trench gate MOSFET is further provided.

公开(公告)号：US20190355846A1

公开(公告)日：2019-11-21

申请号：US16412427

申请日：2019-05-15

Applicant: uPI Semiconductor Corp.

Inventor： Nobuyuki Shirai ,  Chun-Hsu Chang ,  Ming-Hung Chou

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L21/033

Abstract: Provided is a method of forming a trench gate MOSFET. A hard mask layer is formed on a substrate. The substrate is partially removed by using the hard mask layer as a mask, so as to form a trench in the substrate. A first insulating layer and a first conductive layer are formed in the lower portion of the trench. A sacrificial layer is formed on the side surface of the upper portion of the trench, and the sacrificial layer is connected to the hard mask layer. An interlayer insulating layer is formed on the first conductive layer by a thermal oxidation process when the sacrificial layer and the hard mask layer are present. A second insulating layer and a second conductive layer are formed in the upper portion of the trench. A trench gate MOSFET is further provided.