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    Stable low-power analog-to-digital converter (ADC) reference voltage
    2.
    发明授权
    Stable low-power analog-to-digital converter (ADC) reference voltage 有权

    公开(公告)号：US12040815B2

    公开(公告)日：2024-07-16

    申请号：US18126875

    申请日：2023-03-27

    Applicant: AyDeeKay LLC

    Inventor： Christopher A. Menkus ,  Robert W. Kim

    IPC: H03M1/38 ,  H03M1/12 ,  H03M1/14

    CPC classification number: H03M1/38 ,  H03M1/121 ,  H03M1/129 ,  H03M1/14

    Abstract: A conversion circuit that performs analog-to-digital conversion is described. During operation, the conversion circuit receives an input signal. Then, the conversion circuit performs analog-to-digital conversion and provides a quantized output corresponding to the input signal based at least in part on a first power-supply voltage and a second power-supply voltage of the conversion circuit. For example, the quantized output may be based at least in part on a comparison of the input signal to the first power-supply voltage and the second power-supply voltage. Moreover, the first power-supply voltage and the second power-supply voltage may specify a full-scale range of the conversion circuit. When the full-scale range exceeds a second full-scale range associated with reference voltages that are other than the first power-supply voltage and the second power-supply voltage, the quantized output may correspond to a larger number of bits than when the full-scale range equals the second full-scale range.

    Propagation delay compensation and interpolation filter
    3.
    发明授权
    Propagation delay compensation and interpolation filter 有权

    公开(公告)号：US11929757B2

    公开(公告)日：2024-03-12

    申请号：US16949281

    申请日：2020-10-23

    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

    Inventor： Jacques Jean Bertin

    IPC: H03M1/12 ,  G01B7/00 ,  G01B7/30 ,  G01D5/14 ,  G01D11/24 ,  H03M1/48

    CPC classification number: H03M1/129 ,  G01B7/003 ,  G01B7/30 ,  G01D5/145 ,  G01D11/245 ,  H03M1/485

    Abstract: Various embodiments provide a filter for propagation delay compensation and interpolation in encoder digital signal processing. The filter can include a first low pass filter configured to reduce noise of a digital input comprising a measured angular position; a first differentiator configured to receive a filtered digital input and to calculate a speed from a difference in time of the measured angular position and a previous angular position; a second low pass filter configured to reduce noise from the speed; a second differentiator configured to receive a filtered speed and to calculate acceleration using a difference in time of the filtered speed and a previous speed; a third low pass filter configured to reduce noise of the acceleration; and a delay compensator configured to receive the filtered digit input, the filtered speed, and a filtered acceleration, and to calculate a propagation delay compensated digital output.

    INTERLEAVED ADC WITH ESTIMATION OF DSA-SETTING-BASED IL MISMATCH
    4.
    发明申请
    INTERLEAVED ADC WITH ESTIMATION OF DSA-SETTING-BASED IL MISMATCH 审中-公开

    公开(公告)号：US20190013818A1

    公开(公告)日：2019-01-10

    申请号：US16029539

    申请日：2018-07-06

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sthanunathan Ramakrishnan ,  Sashidharan Venkatraman ,  Jaiganesh Balakrishnan ,  Sreenath Narayanan Potty

    IPC: H03M1/12 ,  H03M1/06 ,  H03F1/02

    CPC classification number: H03M1/121 ,  H03F1/0244 ,  H03M1/0626 ,  H03M1/1215 ,  H03M1/129 ,  H03M1/185

    Abstract: An interleaved ADC receives an RX signal attenuated by a DSA based on an active DSA setting, within a range of DSA settings (DSA setting range) corresponding to selectable attenuation steps, the DSA setting range partitioned into a number of DSA setting subranges (DSA subranges). The ADC includes an IL mismatch estimation engine in the digital signal path, with an estimation subrange blanker, and an IL mismatch estimator. The estimation subrange blanker is coupled to receive the IADC data stream, and responsive to a DSA subrange allocation signal to select, in each of successive aggregation cycles, IADC data corresponding to an active DSA setting that is within an allocated DSA subrange (DSA active data within an DSA allocated subrange). The IL mismatch estimator aggregates, during each aggregation cycle, IL mismatch estimation data based on the selected DSA active data within the DSA allocated subrange, generates an estimate of IL mismatch (IL mismatch estimate) based on the aggregated IL mismatch estimation data, generates IL mismatch correction parameters based on the aggregated IL mismatch estimation data, and generates IL mismatch estimate uncertainty data corresponding to an uncertainty in the IL mismatch estimate used to generate the associated IL mismatch correction parameters for the DSA allocated subrange. A DSA statistics collector to collect a distribution of DSA settings over a pre-defined time period (DSA setting distribution statistics). An estimation subrange allocator coupled to receive DSA setting distribution statistics, and the IL mismatch estimate uncertainty data, and to provide to the estimation subrange blanker the DSA subrange allocation signal according to a pre-defined allocation strategy.

    Analog to digital converter error rate reduction
    5.
    发明授权
    Analog to digital converter error rate reduction 有权

    公开(公告)号：US09941896B2

    公开(公告)日：2018-04-10

    申请号：US15294227

    申请日：2016-10-14

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Manar Ibrahim El-Chammas

    IPC: H03M1/34 ,  H03M1/12 ,  H03M1/16

    CPC classification number: H03M1/129 ,  H03M1/164

    Abstract: An analog-to-digital converter (ADC) may include a comparator and a metastability detector. The comparator may be configured to compare an input signal to a reference signal to determine whether the input signal exceeds the reference signal. The comparator may also be configured to output a comparator output based on the determination. An ADC output may be based at least in part on the comparator output. The metastability detector may be coupled to the comparator and may be configured to determine, based at least in part on the comparator output, that the comparator is operating under metastable conditions and may output a metastability detector output.

    ANALOG TO DIGITAL CONVERTOR ERROR RATE REDUCTION
    8.
    发明申请
    ANALOG TO DIGITAL CONVERTOR ERROR RATE REDUCTION 有权

    公开(公告)号：US20170111055A1

    公开(公告)日：2017-04-20

    申请号：US15294227

    申请日：2016-10-14

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Manar Ibrahim EL-CHAMMAS

    IPC: H03M1/46

    CPC classification number: H03M1/129 ,  H03M1/164

    Abstract: An analog-to-digital converter (ADC) may include a comparator and a metastability detector. The comparator may be configured to compare an input signal to a reference signal to determine whether the input signal exceeds the reference signal. The comparator may also be configured to output a comparator output based on the determination. An ADC output may be based at least in part on the comparator output. The metastability detector may be coupled to the comparator and may be configured to determine, based at least in part on the comparator output, that the comparator is operating under metastable conditions and may output a metastability detector output.

    OPTICAL SENSOR ARRANGEMENT AND METHOD FOR GENERATING AN ANALOG OUTPUT SIGNAL
    9.
    发明申请
    OPTICAL SENSOR ARRANGEMENT AND METHOD FOR GENERATING AN ANALOG OUTPUT SIGNAL 有权
    光学传感器布置和产生模拟输出信号的方法

    公开(公告)号：US20160079447A1

    公开(公告)日：2016-03-17

    申请号：US14850908

    申请日：2015-09-10

    Applicant: ams AG

    Inventor： Josef KRIEBERNEGG ,  Christian MAUTNER ,  Herbert LENHARD ,  Manfred LUEGER

    IPC: H01L31/02 ,  G01V8/10

    CPC classification number: H01L31/02016 ,  G01S7/487 ,  G01S17/026 ,  G01S17/10 ,  G01V8/10 ,  H01L31/02002 ,  H03M1/129

    Abstract: An optical sensor arrangement (10) comprises a light sensor (11) that is connected to a summation node (13) and is designed for generating a sensor current (S2), a current source (S2) connected to the summation node (13) and designed to provide a source current (S3), and an integrator (21) that is coupled to the summation node (13) and is designed for generating a first value (VP1) of an integrator signal (S6) by integrating during a first phase (P1) and for generating a second value (VP2) of the integrator signal (S6) by integrating during a second phase (P2). The optical sensor arrangement (10) comprises a sum and hold circuit (31) that is coupled to the integrator (21) and is designed to generate an analog output signal (S7) as a function of a difference of the first value (VP1) and the second value (VP2) of the integrator signal (S6).

    Abstract translation: 光学传感器装置（10）包括连接到求和节点（13）并被设计用于产生传感器电流（S2）的光传感器（11），连接到求和节点（13）的电流源（S2） 并且被设计成提供源极电流（S3），以及积分器（21），其被耦合到所述求和节点（13），并被设计成通过在第一和第二信号中积分来产生积分器信号（S6）的第一值（VP1） 相位（P1），并通过在第二阶段（P2）期间积分来产生积分器信号（S6）的第二值（VP2）。 光传感器装置（10）包括耦合到积分器（21）的和和保持电路（31），并被设计成根据第一值（VP1）的差值产生模拟输出信号（S7） 和积分器信号的第二值（VP2）（S6）。

    Successive approximation analog-to-digital converter and conversion method
    10.
    发明授权
    Successive approximation analog-to-digital converter and conversion method 有权
    逐次逼近模数转换器和转换方法

    公开(公告)号：US09136863B2

    公开(公告)日：2015-09-15

    申请号：US14585812

    申请日：2014-12-30

    Applicant: REALTEK SEMICONDUCTOR CORPORATION

    Inventor： Sheng-Hsiung Lin

    IPC: H03M1/12 ,  H03M1/38

    CPC classification number: H03M1/129 ,  H03M1/468

    Abstract: The present invention discloses a successive approximation analog-to-digital converter, comprising: a capacitor array including a designated capacitor and several sampling capacitors to sample an input signal under a sampling mode; a comparator to compare a first voltage from the capacitor array with a second voltage under a comparison mode and thereby generate a comparison result; a switching circuit to determine the charge amount stored in the capacitor array under the sampling mode and the first voltage under the comparison mode according to a control signal; and a control circuit to generate the control signal according to a sampling setting under the sampling mode and generate the control signal according to the comparison result under the comparison mode. Said designated capacitor does no sampling under the sampling mode, but appropriates the charges of the sampling capacitors under the comparison mode, so as to reduce the effective sampling value.

    Abstract translation: 本发明公开了一种逐次逼近模数转换器，包括：包括指定电容器和几个采样电容器的电容器阵列，以在采样模式下采样输入信号; 比较器，用于在比较模式下将来自电容器阵列的第一电压与第二电压进行比较，从而产生比较结果; 开关电路，用于根据控制信号确定在采样模式下存储在电容器阵列中的电荷量和在比较模式下的第一电压; 以及控制电路，根据采样模式下的采样设定生成控制信号，并根据比较模式下的比较结果生成控制信号。 所述指定电容器在采样模式下不进行采样，而是在比较模式下占用采样电容器的电荷，从而降低有效采样值。

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