Invention Patent
- Patent Title: BICMOS PROCESS
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Application No.: CA2024640Application Date: 1990-09-05
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Publication No.: CA2024640CPublication Date: 1993-07-27
- Inventor: LECHATON JOHN S , SCHEPIS DOMINIC J
- Applicant: IBM
- Assignee: IBM
- Current Assignee: IBM
- Priority: US42436389 1989-10-19
- Main IPC: H01L29/73
- IPC: H01L29/73 ; H01L21/331 ; H01L21/8249 ; H01L27/06 ; H01L29/732 ; H01L21/336
Abstract:
A BiCMOS PROCESS of the Invention A method for manufacturing a BiCMOS device includes providing a semiconductor substrate including first and second electrically isolated device regions. A layer of insulating material is formed over the first device region, and a layer of conductive material is formed conformally over the device. Portions of the conductive layer are removed to leave a base contact on the surface of the second device region and an insulated gate contact over the surface of the first device region. A FET is formed in the first device region having a channel under the insulated gate. A vertical bipolar transistor is formed in the second device region having a base region contacting the base contact.
Public/Granted literature
- CA2024640A1 BICMOS PROCESS Public/Granted day:1991-04-30
Information query
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